Intel Corporation

Anil Agrawal

Yingwen Chen

Fang Yuan

Sarathy Jayakumar

Cameron B McNairy

Eric Gouldey

Satish Muthiyalu

Yi Zeng

Qing Huang

Zhi Yong Chen

Meera Ganesan

Wenjuan Mao

Jenna S Mayfield

Mark Millican

There is disclosed in one example a multi-core computing system configured to provide a hot-swappable CPU0, including: a first CPU in a first CPU socket and a second CPU in a second CPU socket; a switch including a first media interface to the first CPU socket and a second media interface to the second CPU socket; and one or more mediums including non-transitory instructions to detect a hot swap event of the first CPU, designate the second CPU as CPU0, determine that a new CPU has replaced the first CPU, operate the switch to communicatively couple the new CPU to a backup initialization code store via the first media interface, initialize the new CPU, and designate the new CPU as CPUN, wherein N&#x2260;0.

CPU hot-swapping

An example apparatus to monitor memory includes an error manager to compare a first memory location of a first error in the memory to a plurality of memory locations in an error history log, the plurality of memory locations previously identified in the error history log based on errors detected in the memory locations, ones of the memory locations associated with corresponding counters that track the errors detected in the memory locations, and update a first one of the counters corresponding to the first memory location when a first address of the first memory location matches a second address of one of the memory locations in the error history log. The example apparatus further includes a command generator to transmit a command to an error corrector to perform error correction on the first memory location when the first one of the counters satisfies a threshold.

Methods and apparatus to perform error detection and/or correction in a memory device

Techniques and mechanisms for providing error detection and correction for a platform comprising a memory including one or more spare memory segments. In an embodiment, a memory controller performs first scrubbing operations including detection for errors in a plurality of currently active memory segments. Additional patrol scrubbing is performed for one or more memory segments while the memory segments are each available for activation as a replacement memory segment. In another embodiment, a first handler process (but not a second handler process) is signaled if an uncorrectable error event is detected based on the active segment scrubbing, whereas the second handler process (but not the first handler process) is signaled if an uncorrectable error event is detected based on the spare segment scrubbing. Of the first handler process and the second handler process, only signaling of the first handler process results in a crash event of the platform.

Method, apparatus and system for handling data error events with a memory controller

A method for detecting errors in a processing device is disclosed. A data source unit of a processing device transmits data and a qualifier synchronously with the data, the qualifier to indicate the data is uncorrectable. At least one intermediate functional unit in the processing device receives the data and the qualifier. The at least one intermediate functional unit detects the data is uncorrectable based on the qualifier. The at least one intermediate functional unit transmits, without using, the data and the qualifier synchronously with the data to a data consumer unit of the processing device. The data consumer unit receives the data and the qualifier. The data consumer unit detects the data is uncorrectable based on the qualifier. The data consumer unit maintains, without using the data and the qualifier.

Fault handling at a transaction level by employing a token and a source-to-destination paradigm in a processor-based system

Growing community of inventors

Cupertino, CA, United States of America

Anil Agrawal