Intel Corporation

Anil Aggawal

Hong Wang

Edward Thomas Grochowski

Baiju V Patel

Per H Hammarlund

Scott Dion Rodgers

Prashant Sethi

Gautham N Chinya

Shivnandan D Kaushik

Bryant E Bigbee

Xiang Chris Zou

Richard A Hankins

Xinmin Tian

James Paul Held

John Thomas Shen

John P Shen

In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.

Mechanism for instruction set based thread execution on a plurality of instruction sequencers

Mechanism for instruction set based thread execution of a plurality of instruction sequencers

Growing community of inventors

Portland, OR, United States of America

Anil Aggawal