Intel Corporation

Anil Aggarwal

Efraim Rotem

Eliezer Weissmann

Shivnandan D Kaushik

Jeremy J Shrall

Jason W Brandt

Hong Wang

Krishnakanth Venkata Sistla

Guy M Therien

John Thomas Shen

Bryant E Bigbee

Xiang Chris Zou

Baiju V Patel

Prashant Sethi

Gautham N Chinya

Richard A Hankins

Alon Naveh

Per H Hammarlund

James B Crossland

Paul S Diefenbaugh

Andrew D Henroid

John L Reid

Stephen H Gunther

Avinash N Ananthakrishnan

Ankush Varma

Ian M Steiner

Martin Rowland

Matthew M Bace

Scott Dion Rodgers

Russell Jerome Fenger

James Paul Held

Barnes Cooper

Ronny Ronen

Boris Ginzburg

David A Koufaty

Michael Mishaeli

Xinmin Tian

Scott D Hahn

Yuval Yosef

Ed Grochowski

Shiv Kaushik

Rahul Seth

Michael A Rothman

Mohan J Kumar

Ohad Falik

Ittai Anati

Dheeraj R Subbareddy

Ilan Pardo

Eugene Gorbatov

Devadatta V Bodas

Ashok Raj

Robert E Gough

Darrell D Boggs

Sarathy Jayakumar

Sridhar Muthrasanallur

Ganapati Srinivasa

Mark Doran

Doron Orenstein

Jose Andy Vargas

Chris J Newburn

Trung Am Diep

Justin J Song

Shaun M Conrad

Aamer Jaleel

Leena K Puthiyedath

Paolo L Narvaez

Rajesh R Shah

Neelam Chandwani

Avi Mendelson

Gaurav Khanna

Tong Li

Hisham Abu-Salah

Larry O Smith

Oscar P Pinto

Ilya Osadchiy

Michael C Walz

Bruce Schlobohm

Kenzo Van Craeynest

Shivanandan Kaushik

Avi Mendleson

Qingda Lu

The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system.

Collaborative processor and system performance and power management

In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.

User level control of power management policies

In one embodiment, the present invention includes a multicore processor having first and second cores to independently execute instructions, the first core visible to an operating system (OS) and the second core transparent to the OS and heterogeneous from the first core. A task controller, which may be included in or coupled to the multicore processor, can cause dynamic migration of a first process scheduled by the OS to the first core to the second core transparently to the OS. Other embodiments are described and claimed.

Migrating tasks between asymmetric computing elements of a multi-core processor

In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface.

Computing platform interface with memory management

Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof.

Apparatus, system, and method for persistent user-level thread

In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.

Mechanism for instruction set based thread execution on a plurality of instruction sequencers

In one embodiment, the present invention includes a multicore processor with first and second groups of cores. The second group can be of a different instruction set architecture (ISA) than the first group or of the same ISA set but having different power and performance support level, and is transparent to an operating system (OS). The processor further includes a migration unit that handles migration requests for a number of different scenarios and causes a context switch to dynamically migrate a process from the second core to a first core of the first group. This dynamic hardware-based context switch can be transparent to the OS. Other embodiments are described and claimed.

Providing an asymmetric multicore processor system transparently to an operating system

Various embodiments are generally directed to an apparatus, method and other techniques for initiating a transition into a lower power state, determining that a device process prevents a platform processing device from completing the transition to the lower power state and interrupting a processing component from an intermediate power state in order to process the process prior to execution of a defined event.

Techniques for entering a low power state

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Portland, OR, United States of America

Anil Aggarwal