Cypress Semiconductor Corporation

Anil Agarwal

Kamal Dalmia

Mohandas Palathol Mana Sivadasan

P S Mohandas

A high-gain, high-speed differential preamplifier is described, in which a current source is coupled to one input of a differential amplifier and the other input of the differential amplifier is coupled to a sensor. In one implementation, the current source includes a field effect transistor operating in saturation mode and a bipolar junction transmitter in an emitter follower configuration.

High-speed differential preamplifier

One embodiment of the present invention is an improved feedback amplifier circuit having a variable closed loop gain which avoids including switching elements in its feedback network and maintains a constant output voltage window for an input signal having a wide dynamic range. That is, the switching elements are not on the active feedback path (e.g., they are isolated from the active feedback path). In this manner, the gain of the amplifier circuit may be determined only by the feedback resistance which can be more easily controlled through the use of precision resistors. Additionally, by removing the switches from the feedback network, the parasitics associated with each switch may also be removed from the feedback path of the amplifier circuit. Accordingly, the bandwidth of the feedback amplifier circuit can be controlled more effectively. Specifically, the present embodiment avoids locating the switching functionality in the feedback network by changing the output stage of the feedback amplifier circuit. In other words, the switching functionality of the present embodiment is located within the output stage of the feedback amplifier circuit. Furthermore, it is appreciated that the present embodiment provides a way to isolate the unused feedback path of the feedback amplifier circuit which has a variable closed loop gain.

Gain switching scheme for amplifiers with digital automatic gain control

A circuit comprising a first circuit and a state machine. The first circuit may be configured to generate a plurality of state inputs in response to (i) a first clock signal, (ii) a second clock signal delayed from the first clock signal, and (iii) a data signal. The state machine may be configured to generate a pump up signal and a pump down signal in response to (i) said data signal and (ii) a plurality of quadrants defined by a number of possible combinations of the state inputs. The state machine may be further configured to transition between any of the quadrants.

Data frequency detector

An apparatus comprising a first circuit, a second circuit and a logic circuit. The first circuit may be configured generate a first output signal having a first data rate and in response to (i) an input signal having a second data rate and (ii) a clock signal having the second data rate. The second circuit may be configured to generate a second output signal having a third data rate in response to (i) a divided version of the input signal and (ii) the clock signal. The logic circuit may be configured to generate the clock signal in response to (i) the first output signal and (ii) the second output signal.

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Bengaluru, India

Anil Agarwal