Taiwan Semiconductor Manufacturing Comp. Ltd.

Anhao Cheng

Fang-Ting Kuo

Chun-Chang Liu

Yen-Yu Chen

Sheng-Wei Yeh

Yen-Liang Lin

Chung-Lei Chen

Meng-i Kang

An integrated circuit includes a plurality of transistors and an interlevel dielectric layer formed over the transistors. The interlevel dielectric layer includes a first region and a second region with a higher dielectric constant than the first region. The difference in dielectric constant is produced by curing the first region shielding the second region from the curing. Metal signal lines are formed in the first region. Metal-on-metal capacitors are formed in the second region.

Structure and method for interlevel dielectric layer with regions of differing dielectric constant

A semiconductor structure is provided. The semiconductor structure includes a substrate containing a first active region in a first region of the substrate and a second active region in a second region of the substrate, a plurality of first gate structures over the first active region each including a first gate stack having a first high-k gate dielectric and a first gate electrode and first gate spacers surrounding the first gate stack, and a plurality of second gate structures over the second active region each including a second gate stack having a second high-k gate dielectric and a second gate electrode and second gate spacers surrounding the second gate stack. At least a portion of the second gate electrode comprises dopants.

Partial metal grain size control to improve CMP loading effect

The present disclosure is directed to a method for the fabrication of MiM capacitor structures with metallic electrodes having nitrogen-rich metal nitride layers. The method includes depositing a first electrode bilayer on a first interconnect layer disposed on a substrate, where the first electrode bilayer includes a first layer and a second layer with a different nitrogen concentration. The method also includes depositing a dielectric layer on the first electrode bilayer and depositing a second electrode bilayer on the dielectric layer where the second electrode includes a third layer and a fourth layer with a different nitrogen concentration. The method further includes patterning the first electrode bilayer, the dielectric layer, and the second electrode bilayer to form a capacitor structure on the first interconnect layer.

Barrier layer for metal insulator metal capacitors

The present disclosure is directed to a method for the fabrication of MiM capacitor structures with metallic electrodes having nitrogen-rich metal nitride layers. The method includes depositing a first electrode bilayer on a first interconnect disposed on a substrate, where the first electrode includes a first layer and a second layer with a different nitrogen concentration. The method also includes depositing a dielectric layer on the first electrode bilayer and depositing a second electrode bilayer on the first interconnect where the second electrode includes a third layer and a fourth layer with a different nitrogen concentration. The method further includes patterning the first electrode bilayer, the dielectric layer, and the second electrode bilayer to form a capacitor structure on the first interconnect layer.

A method and structure providing a high-voltage transistor (HVT) including a gate dielectric, where at least part of the gate dielectric is provided within a trench disposed within a substrate. In some aspects, a gate oxide thickness may be controlled by way of a trench depth. By providing the HVT with a gate dielectric formed within a trench, embodiments of the present disclosure provide for the top gate stack surface of the HVT and the top gate stack surface of a low-voltage transistor (LVT), formed on the same substrate, to be substantially co-planar with each other, while providing a thick gate oxide for the HVTs. Further, because the top gate stack surface of HVT and the top gate stack surface of the LVT are substantially co-planar with each other, over polishing of the HVT gate stack can be avoided.

Gate structure and methods thereof

A semiconductor device includes a first silicon layer. The semiconductor device includes a plurality of first buried oxide layers embedded in the first silicon layer. The semiconductor device includes a second silicon layer disposed over the plurality of first buried oxide layers. Vertical distances between the plurality of first buried oxide layers and the second silicon layer, respectively, are different.

Semiconductor devices and methods of manufacturing thereof

A semiconductor device includes a first conductive element electrically connected to an interconnect structure, wherein the first conductive element includes a first conductive material. The semiconductor device further includes an RDL over the first conductive element and electrically connected to the first conductive element, wherein the RDL includes a second conductive material different from the first conductive material. The semiconductor device further includes a passivation layer over the RDL, wherein a top portion of a sidewall of the second passivation layer includes a convex curve protruding in a direction parallel to a top surface of the interconnect structure, a width of the top portion at a bottom of the convex curve is less than a width of the top portion at a middle of the convex curve, and the middle of the convex curve is above the bottom of the convex curve.

Semiconductor device having a dual material redistribution line

A method of making a semiconductor device includes depositing a second conductive material over a first conductive material, wherein the second conductive material is different from the first conductive material, and the second conductive material defines a redistribution line (RDL). The method further includes depositing a passivation layer over the RDL, wherein depositing the passivation layer comprises forming a plurality of convex sidewalls, and each of the plurality of convex sidewalls extends beyond an edge of the RDL.

Method of forming semiconductor device having a dual material redistribution line and semiconductor device

A semiconductor device includes a first passivation layer over a substrate. The semiconductor device further includes at least two post passivation interconnect (PPI) lines over the first passivation layer, wherein a top portion of each of the at least two PPI lines has a rounded shape. The semiconductor device further includes a second passivation layer configured to stress the at least two PPI lines. The semiconductor device further includes a polymer material over the second passivation layer and filling a trench between adjacent PPI lines of the at least two PPI lines.

Semiconductor device having a redistribution line

A method of making a semiconductor device includes plating a first conductive material over a first passivation layer, wherein the first conductive material fills an opening in the first passivation layer and electrically connects to an interconnect structure. The method further includes planarizing the first conductive material, wherein a top surface of the planarized first conductive material is coplanar with a top surface of the first passivation layer. The method further includes depositing a second conductive material over the first passivation layer, wherein the second conductive material is different from the first conductive material, and the second conductive material is electrically connected to the first conductive material in the opening. The method further includes patterning the second conductive material to define a redistribution line (RDL).

Method of forming semiconductor device having a dual material redistribution line

A method of manufacturing a semiconductor device includes depositing a first passivation layer over a substrate, depositing a conductive material over the first passivation layer, patterning the conductive material to form a redistribution layer (RDL) structure, and depositing a second passivation layer configured to change a shape of a top portion of the RDL structure.

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Hsinchu, Taiwan

Anhao Cheng