Apple Inc.

Anh T Hoang

Brian S Park

Patrick D McNamara

Ravi Karapatti Ramaswami

Gregory Stuart Scott

Raman S Thiara

Geertjan Joordens

Samy R Makar

Vasu P Ganti

Kwang M Lee

Meng C Chong

John P Gonzalez

A method and apparatus for power glitch detection in IC's is disclosed. In one embodiment, a method includes a detection circuit in an IC detecting a voltage transient wherein a value of a supply voltage has at least momentarily fallen below a reference voltage value. Responsive thereto, the detection circuit may cause a logic value to be stored in a register indicating that the detection circuit has detected the supply voltage falling below the reference voltage. The IC may include a number of detection circuits coupled to the register, each of which may provide a corresponding indication of detecting the supply voltage falling below the reference voltage. The detection circuits may be placed at different locations, and thus reading the register may yield information indicating the locations where, if any, such voltage transients occurred.

Method and apparatus for power glitch detection in integrated circuits

A self-test loopback apparatus for an interface is disclosed. In one embodiment, a bidirectional interface of an integrated circuit includes a transmitter coupled to an external pin, a first receiver coupled to the external pin, and a second receiver coupled to the external pin. During operation in a test mode, the first receiver may be disabled. The transmitter may transmit test patterns generated by a built-in self-test (BIST) circuit, and compare those test patterns to patterns received by the second receiver. The second receiver may be implemented as a Schmitt trigger (wherein the first receiver may be a standard single-bit comparator). When operating in functional mode, the second receiver may be disabled.

Noise rejection for built-in self-test with loopback

A system and method for testing circuits. A generated input voltage waveform for a first phase of a test may use transitions with a voltage swing between expected low and high trigger points for an integrated circuit (IC) with hysteresis. A generated input voltage waveform for a second phase of the test may use transitions with a voltage swing between the expected low trigger point and a high sub-threshold value. The high sub-threshold value may be a tolerable voltage difference below the expected high trigger point. A generated input voltage waveform for a third phase of the test may use transitions with a voltage swing between the expected high trigger point and a low sub-threshold value. The low sub-threshold value may be a tolerable voltage difference above the expected low trigger point. The expected trigger points and sub-threshold values may be found from earlier characterization studies for the IC.

Method for testing integrated circuits with hysteresis

A method and apparatus for detecting clock glitches during at-speed testing of integrated circuits is disclosed. In one embodiment, an integrated circuit includes a scan chain having a number of scan elements coupled in a series configuration. Each of the scan elements is coupled to receive a clock signal that may be cycled during a test operation. A subset of the scan elements are arranged to form, along with other components, a counter. Test stimulus data shifted into the scan chain to perform a test may include an initial count value that is shifted into the scan elements of the counter. When the test is performed, the count value is updated responsive to cycling of the clock signal. The updated count value is shifted from the counter along with other test result data, and may be used to determine if the number of clock cycles received during the test.

Apparatus and method for clock glitch detection during at-speed testing

A system and method for efficiently performing timing characterization of regions of an integrated circuit. An integrated circuit has monitors distributed in different physical regions across its die. Each monitor includes timing characterization and self-test circuitry. This circuitry includes one or more tunable delay lines used during timing measurements. The circuitry verifies the tunable delay lines are defect free prior to the timing measurements. If defects are detected, but tunable delay lines may still be used, a scaling factor may be generated for a failing tunable delay line. The scaling factor may be used during subsequent timing measurements to maintain a high accuracy for the measurements. The timing measurements may determine a particular physical region of the die provides fast or slow timing values. The resulting statistics of the timing measurements may be used to change an operational mode of the IC in at least the particular region.

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Fremont, CA, United States of America

Anh T Hoang