General Automation, Inc.

Davin Computer Corporation

David Computer Corporation

Angus McLagan

Chong S Un

Gei-Jon Pao

John J Pearce

David H Methvin

Kirk B Cummings

A register architecture for a computer in which a plurality of banks of general purpose registers are used in the register files. Each of the multiple register banks is dedicated to a different user, with one of the register banks being dedicated to servicing interrupts and another of the register banks being dedicated to the operating system of the computer in which the register architecture is incorporated. Associated with each of the register banks is a smaller register bank of status registers in which information concerning the status of the computer is stored.

Multiple sliding register stacks in a computer

A data communications system for a computer for transferring data between the memory of the computer and one or more peripheral devices without requiring an interrupt context switch. The data communications system includes a number of specialized registers in the central processing unit of a computer, a computer memory, a data storage location associated with one or more peripheral devices, and a bus connecting the data storage location to the memory. The specialized registers in the central processing unit are dedicated exclusively to processing data transfers between the memory and the data storage location associated with the peripheral devices. Data transfers between the computer memory and the data storage location associated with the peripheral devices are made under the control of the central processing unit with the use of the special registers without the execution of an interrupt context switch.

Automatic data channels for a computer system

A processor is disclosed for use in a computer system for comparing a number of bytes simultaneously in order to locate a control character in a string of data. The processor includes a register for holding the data bytes, a register for storing the control characters, a comparison circuit for simultaneously comparing the bytes of the first register with the bytes of the second register, and a circuit for generating indicator bits when a match has been found between the two registers. Microcode instructions cause the system to branch to a predetermined memory location when the control character has been located and to branch to a second predetermined memory location when no control character is found in the data string. In another aspect, a parallel string processor for a minicomputer for searching portions of text or binary bit strings for the presence of desired words or bit strings. The processor includes a first register in which a keyword string is stored and a pair of interconnected shift registers in which the string to be searched for the presence of the keyword is stored. An arithmetic logic unit compares the contents of the first register with one of the shift registers to determine whether the keyword is present in the portion of the string being searched. After each such comparison, the contents of the interconnected shift registers are shifted with respect to the keyword stored in the first register. When the processor is searching for the presence of a keyword having a predetermined number of bytes, the contents of the shift registers are shifted one bytes at a time, and when the processor is searching for the presence of a keyword having a predetermined number of bits, the contents of the shift registers are shifted one bit at a time.

Parallel string processor and method for a minicomputer

A priority arbitration circuit for resolving priority between a plurality of master devices which compete for access to one or more slave devices over a common bus. All master devices share a common Request line and a common Busy line. Priority is passed along serially from one device to another in sequence until all pending requests have been serviced, after which priority reverts to an initial device. The first device to issue a request gains priority. Simultaneous requests are resolved in the order in which the devices are connected in the priority chain. A device having a local request and receiving priority on the priority chain sets the Busy signal to lock out all other devices.

Asynchronous priority circuit for controlling access to a bus

A multiprocessor system is described in which a plurality of central processor units share the same main memory over a common asynchronous bus. Each central processor directs all memory requests to its own high speed cache memory. If the request is to read data from memory, the cache memory control determines if the addressed data is present in the cache memory. If so, the data is transferred to the processor without accessing main memory over the bus. If the data is not present in the cache memory, the cache memory control gains access to the bus by a priority circuit and reads out the data from memory, storing the data in the cache memory at the same time that it transfers the data to the processor. If the memory request by the processor is to write data in memory, the cache memory control gains access to the bus and initiates a data store in the main memory. At the same time, the cache memory control determines if the existing data being overwritten at the addressed location in main memory is present in the cache memory. If so, it updates the data in the cache memory at the same time it writes the data in main memory.

Growing community of inventors

Newport Beach, CA, United States of America

Angus McLagan