Integrated Device Technology, Inc.

Angus David Starr MacAdam

Robert H Bishop

Brian Scott Darnell

Alexander P Goldhammer

David Stuart Gibson

Frank Matthews

Bruce Lorenz Chin

Mike Farrell

Justin Preyer

Alan Wolfram Glaser

Stephen Christopher DeMarco

A packet switch includes virtual output queues for mapping data units of data packets from input ports to output ports of the packet switch. The packet switch selects virtual output queues based on old age indicators of the virtual output queues and routes data units mapped at heads of the selected virtual output queues to output ports of the packet switch. Further, the packet switch may identify a data unit of a multicast data packet mapped at the head of more than one virtual output queue and contemporaneously route the data unit to more than one output port. Additionally, the packet switch may update an old age indicator to indicate a virtual output queue is old if the virtual output queue maps an unserviceable data unit of a multicast data packet and the same data unit is mapped at the head of a selected virtual output queue.

Old virtual queues technique for routing data packets in a packet switch

A packet switch includes individual route tables for ports of the packet switch. Each route table is associated with a port and individually maps a destination identifier of a data packet received at the port to another port in the packet switch. In some embodiments, the packet switch routes a data packet to an intermediate device based on a destination identifier in the data packet. The intermediate device services the data packet and sends the data packet, which includes the same destination identifier, back to the packet switch. In turn, the packet switch routes the data packet to a destination device based on the destination identifier in the data packet. The destination device terminates the data packet and may further service the data packet. In this way, the packet switch routes the data packet to both the intermediate device and the destination device based on the same destination identifier.

Packet switch with port route tables

A packet switch including input ports having various input bandwidths initializes credit values for the input ports. An arbiter of the packet switch selects input ports based on the credit values and routes data packets from the selected input ports to a switch fabric of the packet switch. The switch fabric routes data packets from the selected input ports to output ports of the packet switch. Moreover, the arbiter modifies the credit value of each selected input port based on the latency for routing the data packet from the selected input port to the switch fabric. In this way, the arbiter promotes fairness in routing additional data packets through the packet switch. In some embodiments, the switch fabric includes a buffered crossbar and the arbiter modifies credit values of crosspoints in the buffered crossbar based on the latency for routing data packets from the crosspoints to the output ports.

Packet latency based arbitration technique for a packet switch

A communication system includes a packet switch that routes data packets between endpoint devices in the communication system through virtual channels. The packet switch includes output ports each having a link bandwidth for outputting data packets. Each virtual channel is associated with an output port and is allocated a portion of the link bandwidth of the output port. The packet switch receives a data packet identifying a virtual channel at an input port, selects another virtual channel associated with the input port, routes the data packet through the packet switch, and outputs the data packet from the packet switch by using the selected virtual channel. Additionally, the packet switch may select a reliable transmission protocol, a continuous transmission protocol, or a pseudo-continuous transmission protocol for outputting the data packet from the packet switch. In some embodiments, the packet switch modifies the data packet to indicate the selected virtual channel.

Packet switch with configurable virtual channels

A communication system that includes a packet switch having a buffered crossbar for routing data packets from input ports to output ports of the packet switch. The buffered crossbar stores a data packet received from an input port based on a clock signal of a clock domain and sends the data packet to an output port of the packet switch based on a clock signal of another clock domain. In this way, the buffered crossbar functions as a clock domain boundary between the input port and the output port. Moreover, the frequency of one or both of the clock signals may be selected to minimize power consumption in the packet switch or to select a tradeoff between power consumption and performance of the packet switch.

Power reduction technique for buffered crossbar switch

A packet switch includes a pointer table for mapping locations in an input data buffer to locations in an output data buffer. The processor generates an output data packet based on data portions in the input data buffer and based on the pointer table. The output data buffer stores data portions of the output data packet successively in a sequential order and can output the data portions of the output data packet successively in a sequential order. The pointer table may be configured to reduce the latency or reduce the power consumption of the packet switch.

System and method of constructing data packets in a packet switch

A packet switch including input ports and output ports allocates an output bandwidth of each output port among virtual channels based on bandwidth allocations values corresponding to the virtual channels and a bandwidth precision value of the output port. The bandwidth precision value indicates a number of bandwidth precision bits, which may be outside a bandwidth reservation precision range specified in a serial RapidIO standard. The packet switch receives data packets compliant with the serial RapidIO standard at the input ports, identifies an output port for each data packet, and selects input ports based on the output ports of the data packets. Further, the packet switch routes a data packet from each selected input port to the output port of the data packet, and the output port outputs the data packet by using the output bandwidth of the output port allocated to the virtual channel identified by the data packet.

Packet switch with configurable bandwidth allocation precision

A packet switch includes an error management module in addition to various components that facilitate routing of data packets through the packet switch. The components generate error codes indicating errors occurring in the packet switch and provide the error codes to the error management module. The error management module select error codes generated by the components and generates an error log based on the selected error codes. Each component is inhibited from providing the same error code to the error management module more than once until the component receives an acknowledgement for that error code from the error management module. A user can access the error log during operation of the packet switch to monitor performance of the packet switch.

Error management system and method for a packet switch

A packet switch includes a packet processor for processing data packets. The packet processor receives a data packet including a data payload, identifies data portions in the data payload, and determines a destination address for each data portion. Additionally, the packet processor constructs data packets, each including a data portion and the destination address of the data portion. The packet processor then routes each of the constructed data packets based on a destination identifier of the constructed data packet. An external recipient can then store the data portions of the constructed data packets based on the data addresses in the constructed data packets.

Packet processing in a packet switch with improved output data distribution

Time-slot interchange (TSI) switches include a data memory having first entries therein that contain serial data received by the switch and a connection memory having second entries therein. When programmed, these second entries contain addresses of a plurality of the first entries in the data memory and switching modes that have been assigned to the plurality of the first entries. A control circuit is also provided to automatically program a block of the second entries in the connection memory with updated switching modes during an efficient burst program mode of operation. An internal bypass feature is also provided to support efficient testing/debugging of downstream devices in a communications path.

Time-slot interchange switches having efficient block programming and on-chip bypass capabilities and methods of operating same

Time-slot interchange (TSI) switches include an input buffer that is configured to receive at least first and second groups of serial input data streams and an output driver that is configured to generate at least first and second groups of serial output data streams. A control circuit is also provided. This control circuit is electrically coupled to the input buffer and output driver. The control circuit is configured to provide programmable group-based output drive enable control to the at least first and second groups of serial output data streams that is independent of per-channel output stream programming. This per-channel output stream programming is defined by mode bits within the switch's connection memory.

Time-slot interchange switches having group-based output drive enable control and group-based rate matching and output enable indication capability

An integrated circuit memory device includes a memory, a read control circuit operatively associated with the memory and configured to produce data from the memory responsive to an externally-applied input clock signal, and an output latch configured to transfer data at an input thereof to an output pad of the memory device responsive to an externally-applied output clock signal. The device further includes a clock domain alignment circuit configured to receive the data produced by the memory and to responsively provide the data at the input of the output latch based on relative timing of the input clock signal and the output clock signal.

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Suwanee, GA, United States of America

Angus David Starr MacAdam