Micron Technology Incorporated

Other

Micron Semiconductor, Inc.

Angus C Fox, Iii

Fernando N Gonzalez

Gurtej S Sandhu

Warren M Farnworth

Trung Tri Doan

Mark E Tuttle

Thomas Arthur Figura

Hugh E Stroupe

An emergency control system permits an aircraft to recover from a catastrophic loss of cabin pressure even if the pilot becomes incapacitated before he is able to activate an emergency oxygen system. An autopilot system is programmed for rapid descent, in response to a cabin depressurization condition detected by an air pressure sensor, to a flight level where there is sufficient oxygen in the atmosphere to sustain full consciousness. When in the rapid descent mode, the autopilot cuts engine power to idle, reduces the angle of attack, maximizes parasitic drag, and initiates a maximum descent rate without exceeding the aircraft's design limitations. As the aircraft approaches a lower altitude capable of sustaining full human consciousness, the autopilot system increases the angle of attack, reduces parasitic drag, and increases engine power, thereby causing the aircraft to fly level at the lower altitude until the pilot reasserts control of the aircraft.

Autopilot for aircraft having automatic descent function in the event of cabin depressurization

This invention is a process for fabricating a DRAM capacitor having an annularly-grooved, cup-shaped storage-node plate and a cell plate which covers both inner and outer surfaces of the storage-node plate. A plurality of oxide layers having alternately-varying composition are deposited on top of an in-process DRAM array to form a single sacrificial mold layer. In a preferred embodiment of the invention, ozone TEOS oxide is one of the alternately-varying layers, and plasma-enhanced TEOS oxide is the other. Ozone TEOS oxide etches more rapidly than does plasma-enhanced TEOS oxide, and both types of TEOS oxide are etchable with respect to polycrystalline silicon. Following the deposition of the sacrificial mold layer, the mold layer is patterned and anisotropically etched to form a mold opening in the mold layer. Contact to the storage node of the cell access transistor is made at the bottom of the mold opening. The mold layer is then subjected to a wet etch which etches the alternating oxide layers within the mold layer at different rates. Because of the different etch rates, a plurality of grooves are formed on the surface of the mold opening. A polysilicon layer is then deposited which covers the upper surface of the mold layer and conformally lines the mold opening. Following the removal of the polysilicon layer from the upper surface of the mold layer, the mold layer is etched away so as to expose the outer surface of the polysilicon layer remnant that is to be the storage-node capacitor plate. The capacitor is then completed in a conventional manner.

Process for manufacturing a DRAM capacitor having an annularly-grooved,

The present invention is a process for forming diffusion areas and field isolation regions on a silicon substrate, by the steps of: growing a field oxide layer on the surface of the substrate; forming a mask pattern which exposes a plurality of spaced-apart regions on the surface of the field oxide layer; removing portions of the field oxide layer in the exposed, spaced-apart regions with an anisotropic etch so as to leave a cavity in each spaced-apart region, each cavity having as its floor an exposed region of the silicon substrate, and having vertical walls of field oxide; angularly chamfering the rim of each cavity with a facet etch; and filling each cavity with silicon using selective epitaxial growth, and using the floor of each cavity as the seed crystal for such growth.

Sub-micron diffusion area isolation with Si-SEG for a DRAM array

A method is provided for forming inter-electrode spacers useful in flat panel display devices which comprises placing a mold on a first electrode plate. The mold has openings with corresponding diameters. The mold is coated with a conformal film which lines the openings, thereby decreasing the diameters of the openings. The openings are filled with a glass material. The conformal film is selectively removed, and the mold is separated from the electrode.

Method for fabricating spacer support structures useful in flat panel

Sub-micron diffusion area isolation with SI-SEG for a DRAM array

A method and apparatus for improving planarity of chemical mechanical planarization of semiconductor wafers. The wafer is affixed to the planar surface of a wafer carrier. A planar platen, on which is mounted a polishing pad, is moved about in a plane parallel to the pad surface with either an orbital, fixed-direction vibratory, or random-direction vibratory motion. In one embodiment of the invention, pressure between the surface of the wafer to be polished and the moving polishing pad is generated by the force of gravity acting on at least the wafer and the carrier; in another it is provided by a mechanical force applied normal to the wafer surface. The polishing pad is wetted with a slurry having abrasive particles suspended in a liquid which may be chemically reactive with respect to at least one material on the wafer.

Method and apparatus for improving planarity of chemical-mechanical

A high-density package containing identical multiple IC chips is disclosed. The package is assembled from submodules interleaved with frame-like spacers. Each submodule comprises a rectangular, wafer-like substrate. The substrate has a planar metalization pattern, comprising conductive traces, on its upper surface. A single memory chip is face-bonded to this metalization pattern. Each of the traces extends from beneath a chip bonding pad, with which it is in electrical communication, and runs to the substrate periphery, where it terminates in one or more solderable package interconnection pads (PIP's). Each PIP is associated with a single substrate via, which extends through the pad to the lower surface of the substrate. During package assembly, a spacer is adhesively bonded to the peripheral upper surface of each sub-module, with the frame surrounding the chip. The spacer also has a plurality of vias which are coincident and coaxial with the substrate vias, with the spacer vias being of larger diameter. Each spacer-equipped module is then adhesively bonded to the others to form a stack. The upper-most spacer-equipped module is fitted with a non-metalized (capping) substrate. In order to electrically interconnect the related traces of all sub-modules, the package is placed in a solder bath, and a partial vacuum is applied simultaneously to one end of all tubes formed from the coincident, stacked vias, filling them with molten solder.

High-density electronic package comprising stacked sub-modules which are

A process, compatible with reduced-pitch masking technology, for creating a metal etch mask that will not erode in a halogenated-plasma etch environment. The process begins by creating an isolation layer (preferably of silicon dioxide) on top of the layer to be etched (typically a silicon substrate). A thin layer of a metal selected from a group consisting of cobalt, nickel, palladium, iron, and copper is then deposited on top of the isolation layer. A hard-material mask (preferably of silicon dioxide) is then created on top of the metal layer as though it were to be the final etch mask. A layer of polysilicon is then blanket deposited on the surface of the in-process wafer. The polysilicon layer must be sufficiently thick to entirely convert exposed regions of the underlying metal layer to silicide during a subsequent elevated temperature step. Only metal in regions not covered by the hard-material mask is converted to silicide. Unreacted polysilicon is then removed with a wet polysilicon etch, followed by the removal of the hard-material mask with a wet etch selective for silicon dioxide over the existent metal silicide, followed by removal of the metal silicide with a wet etch selective for silicide over silicon dioxide to avoid undercutting the oxide isolation layer beneath the metal layer remnants. The metal layer remnants constitute a metal mask which precisely duplicates the pattern of the hard-material mask.

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Boise, ID, United States of America

Angus C Fox, Iii