Micron Technology Incorporated

Other

Stmicroelectronics S.r.l.

Skhynix Inc.

Hynix Semiconductor Inc.

Politecnico Di Milano

Angelo Visconti

Silvia Beltrami

Giorgio Servalli

Mattia Robustelli

Andrea Locatelli

Richard Edward Fackenthal

Mauro Bonanomi

Seiichi Aritome

Daniele Balluchi

Jahanshir J Javanifard

Aswin Thiruvengadam

William A Melton

Jonathan J Strand

Massimo Ernesto Bertuccio

Riccardo Pazzocco

Laura Tatiana Czeppel

Ferdinando Bedeschi

Daniele Vimercati

Marco Sforzin

Umberto Di Vincenzo

Giovanni Campardo

Riccardo Muzzetto

Gian Pietro Vanalli

Kevin T Majerus

Soo Jin Wi

Stefano Corno

Soojin Wi

Christian Monzio Compagnoni

Alessandro Sottocornola Spinelli

Luca Chiavarone

Alexey Petrushin

Durai Vishak Nirmal Ramaswamy

John David Porter

Paolo Amato

Paolo Tessariol

Marcello Mariani

Emilio Camerlenghi

Alessandro Calderoni

Amitava Majumdar

Alessandro Grossi

Tecla Ghilardi

Massimiliano Patriarca

Daniele Ielmini

Garth N Grubb

Giorgio Cellere

Alessandro Paccagnella

Slivia Beltrami

Pietro Guzzi

Senthil Murugan Thangaraj

Miguel Mares

Alessandro Spinelli

Correctable error pattern information for a memory device can be based on data received from or using a data pin of the memory device. The memory device can include, for example, a DRAM device comprising an array of memory cells. Based on the error pattern information, firmware or software can be used to identify respective physical portions of the array comprising data with correctable errors. In an example, one or more fault locations in the memory device can be identified, the fault location corresponding to multiple cells in the array and comprising the data with correctable errors. In response to identifying the fault location in the array, one or more memory pages corresponding to the location(s) can be offlined or removed from an addressable memory space. In an example, the memory device comprises a portion of a compute express link (CXL) system.

Memory failure prediction and mitigation

Methods, systems, and devices for data masking for memory are described. A memory device may set multiple data masking flags for associated memory array(s) at power-up. Each data masking flag may be associated with a respective page of memory cells and may indicate whether the data stored in the respective page is masked data, or whether the data is new, unmasked data. Data existing at a previous power-down may be masked until an initial write or activate command has been performed on the page after power-up, where the initial write or activate command may result in writing masked data, write data, or a combination thereof to the page. After previously stored data is overwritten to a page, the flag associated with the page may be reset, which may indicate that data stored at the page is available to be read.

Data masking for memory

Systems, apparatuses, and methods related to memory activation timing management are described herein. In an examples, memory activation timing management can include receiving a first command associated with a set of memory cells, activating the set of memory cells to perform a memory access responsive to the first command, pre-charging the set of memory cells associated with the first command, receiving a second command associated with the set of memory cells, determining that the set of memory cells associated with the first command is a recently activated set of the plurality of sets of memory cells, imparting a delay, and applying a sensing voltage to the set of memory cells associated with the second command to perform a memory access responsive to the second command.

Memory activation timing management

Methods, systems, and devices for differential storage in memory arrays are described. A memory device may include pairs of memory cells configured to store a single logic state (e.g., a single bit of information). Additionally, the memory device may include sense amplifiers configured to sense the logic state based on a difference between a voltage of a first ferroelectric memory cell of the pair of memory cells and a voltage of a second ferroelectric memory cell of the pair of memory cells. In one example, the memory device may include pairs of memory cells within a single memory array on a single level. Here, each memory cell pair may include a memory cells that are each coupled with a same word line and plate line. Additionally, each memory cell pair may include memory cells each coupled with different digit lines.

Differential storage in memory arrays

Methods, systems, and devices for robust functionality for memory management associated with high-temperature storage are described. A memory device may apply a pattern (e.g., an imprint conditioning or deletion pattern) to at least a portion of memory cells of a memory array associated with a memory device before or after a power state procedure. The memory device may determine the pattern from various possible patterns, where the pattern may indicate a data state for each memory cell of the portion of memory cells. The pattern may indicate a same data state for each memory cell, an alternating data state for each memory cell, or an asymmetric switching pattern over a plurality of cycles, or any combination thereof. The memory device may write a respective logic value to at least some of the one or more memory cells of the portion of memory cells according to the pattern.

Robust functionality for memory management associated with high-temperature storage and other conditions

Methods, systems, and devices for biasing a memory cell during a read operation are described. For example, a memory device may bias a memory cell to a first voltage (e.g., a read voltage) during an activation phase of a read operation. After biasing the memory cell to the first voltage, the memory device may bias the memory cell to a second voltage greater than the first voltage (e.g., a write voltage) during the activation phase of the read operation. After biasing the memory cell to the second voltage, the memory device may initiate a refresh phase of the read operation. Based on a value stored by the memory cell prior to biasing the memory cell to the first voltage, the memory device may initiate a precharge phase of the read operation.

Memory cell biasing techniques during a read operation

Systems and methods described herein may enable memory maintenance operations to be performed on a memory device in compliance with a time interval having a duration based on a temperature of the memory device. A system may include a memory device and a memory controller communicatively coupled to the memory device. The memory controller may receive a temperature measurement indicative of a present temperature of the memory device and determine a memory management interval based on the temperature measurement. The memory controller may perform a memory management operation based on the memory management interval. Sometimes, the memory controller powers on the memory device to perform the memory management operation on the memory device.

Systems and methods to manage memory during power down and storage

Methods, systems, and devices for read operations based on a dynamic reference are described. A memory device may include a set of memory cells each associated with a capacitive circuit including a first and second capacitor. After receiving a read command, the memory device may couple each capacitive circuit with a respective memory cell (e.g., to transfer a charge stored by each respective memory cell to a capacitive circuit) and may couple the second capacitor of each capacitive circuit to a reference voltage bus. Thus, a reference voltage on the reference voltage bus may be based on an average charge across the second capacitors of each capacitive circuit. The memory device may then compare a charge stored by the first and second capacitors of each capacitive circuit with the reference voltage bus and may output a set of values stored by the set of memory cells based on the comparing.

Read operations based on a dynamic reference

Systems and methods described herein may enable a memory system to selectively provide a signal boost to a word line to precharge the word line. A memory device may include voltage shaping circuitry and a memory controller. The memory controller may cause the voltage shaping circuitry to adjust a characteristic of a word line select control signal transmitted via the word line prior to the word line select control signal being transmitted to a memory cell.

Word line precharging systems and methods

At least one portion of a memory array may be arranged to provide high density non-volatile random access memory (HIGH DENSITY NON-VOLATILE RAM) while at least one other portion of the memory array may be arranged to provide dynamic random access memory (DRAM)-like memory. In some examples, the memory array may be arranged by programming one or more configuration devices. In some examples, the configuration device may include one or more switches to couple one or more memory cells to a sense amplifier. In some examples, the configuration device may include fuses and/or antifuses to couple one or more memory cells to a sense amplifier. In some examples, the portions of the memory array may be reconfigurable from one arrangement to another arrangement.

Apparatuses, systems, and methods for configurable memory

Systems and methods described herein may enable a memory system to selectively provide a signal boost to a memory cell in response to a change in operating condition, like a change in temperature. The systems and methods may include determining to generate a signal boost for a first duration of time and in response to determining to generate the signal boost, generating the signal boost causing an increase in voltage applied to a signal line coupled to a memory cell. The systems and methods may further include, after the first duration of time, ceasing generation of the signal boost.

Digit line voltage boosting systems and methods

Methods, systems, and devices for managing memory based on access duration are described. A memory device may include a first set of memory cells resilient against access durations of a first duration and a second set of memory cells resilient against access durations of a shorter duration. A command for accessing the memory device may be received. The command may be associated with an access duration. Whether to access, as part of executing the command, the first set of memory cells or the second set of memory cells may be determined based on the access duration. The first set of memory cells may be accessed, as part of executing the command, based on the access duration being greater than a threshold duration. Or the second set of memory cells may be accessed based on the access duration being less than or equal to the threshold duration.

Managing memory based on access duration

Provided is a computing system including a memory system in communication with a host, to store data therein. The memory system includes a memory having a plurality of memory components coupled to the controller via a memory interface; and a memory controller configured to communicate with the memory to control data transmission and performing scrubbing operation of the memory components and detecting a region of the memory to be sanitized and performing a sanitization operation of the detected region to prevent the occurrence of failure.

Predictive sanitization of an array of memory with capacitive cells and/or ferroelectric cells

Methods, systems, and devices for memory cell biasing techniques are described. A memory cell may be accessed during an access phase of an access operation. A pre-charge phase of the access phase may be initiated. The memory cell may be biased to a voltage (e.g., a non-zero voltage) after the pre-charge phase. In some examples, the memory cell may be biased to the voltage when a word line is unbiased and the memory cell is isolated from the digit line.

Memory cell biasing techniques

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Appiano Gentile, Italy

Angelo Visconti