Stmicroelectronics S.r.l.

Stmicroelectronics International N.v.

Angelo Scuderi

Salvatore Scaccianoce

Giorgio Maiellaro

Antonino Calcagno

Nicola Marinelli

Giuseppe Palmisano

Antonino Scuderi

Francesco Carrara

Angela Bruno

Luca La Paglia

Egidio Ragonese

Gaetano Cosentino

Giovanni Cali

Santi Concetto Pavone

Daniele Tripoli

Davide Nicolo Fortunato

Gesualdo Alessi

Marco Vinciguerra

A circuit, integrated circuit, and radar system implementing a highly coupled inductor design for a multi-core oscillator is provided. An example circuit may include a plurality of inductors, each inductor including: a first inductor portion and a second inductor portion electrically connected in series. In some embodiments, for each inductor, the first inductor portion may be magnetically coupled to a first or second inductor portion of a first coupling inductor of the plurality of inductors, and the second inductor portion may be magnetically coupled to a first or second inductor portion of a second coupling inductor of the plurality of inductors, where the first coupling inductor and the second coupling inductor are different inductors.

Highly coupled inductor design for reducing area and power consumption of a multi-core oscillator

An electronic device has a plurality of integrated circuits fixed to a support between transmitting and receiving antennas. An integrated circuit generates a synchronization signal supplied to the other integrated circuits. Each integrated circuit is formed in a die integrating electronic components and overlaid by a connection region according to the Flip-Chip Ball-Grid-array or embedded Wafer Level BGA. A plurality of solder balls for each integrated circuit is electrically coupled to the electronic components and bonded between the respective integrated circuit and the support. The solder balls are arranged in an array, aligned along a plurality of lines parallel to a direction, wherein the plurality of lines comprises an empty line along which no solder balls are present. A conductive synchronization path is formed on the support and extends along the empty line of at least one integrated circuit, between the solder balls of the latter.

Integrated circuit and electronic device comprising a plurality of integrated circuits electrically coupled through a synchronization signal

A voltage-controlled oscillator in a phase-locked loop circuit is calibrated via a dichotomous search in a set of candidate frequency bands via a sequence of subsequent halving steps that produce reduced subsets of the set of candidate frequency bands. The reduced subsets have respective upper bound values and lower bound values, as well as central values. The central value of the subset resulting from the halving step of index i in the sequence is a function of the average of the upper bound value and the lower bound value of the subset resulting from the halving step of index i−1 in the sequence.

Calibration method for phase-locked loops and related circuit

A radio-frequency receiver includes built-in-self-test (BIST) circuitry which generates a self-test signal. A local oscillator signal is divided. A self-test oscillation signal is generated, based, at least in part, on the frequency-divided local oscillation signal. The self-test signal is generated based on the self-test oscillation signal. The BIST circuitry includes a divider, which divides the self-test oscillation signal. The frequency-divided local oscillation signal and the divided self-test oscillation signal are used to perform one or more of generating the self-test oscillation signal and controlling the generation of the self-test oscillation signal. The radio-frequency receiver may be an automotive radar receiver.

Method of generating self-test signals, corresponding circuit and apparatus

An integrated circuit includes a semiconductor substrate, electronic components integrated in the semiconductor substrate, an electric connection structure overlying the semiconductor substrate, and an conductive region, with elongated shaped, having a first and a second end. The conductive region is formed in the electric connection structure, extends over an entire length of the substrate and is not directly electrically connected to the electronic components. A first and a second synchronization connection element are electrically coupled to the first end and to the second end, respectively, of the conductive region and have each a respective synchronization connection portion facing the coupling face.

Integrated circuit and electronic device comprising a plurality of integrated circuits electrically coupled through a synchronization signal routed through the integrated circuit

Systems and methods for switching on and off a power amplifier including a signal input receiving an input signal and a signal output providing an output signal. The power amplifier includes a control input receiving a gain control signal indicating a requested gain and a control input receiving a mute control signal indicating whether the signal output should be switched on or switched off. A control unit determines whether the signal output of the power amplifier should be switched on and/or off, and if switched on receives data identifying a switch-on ramp and if switched off receives data identifying a switch-off ramp. The control unit generates the mute control signal to switch on the signal output of the power amplifier on or off, and generates the gain control signal as a function of the data identifying the switch-on or switch-off ramp to thereby increase or decrease the gain control signal.

Method of switching on and off a power amplifier, related power amplifier circuit, system and computer program product

An oscillator circuit may include a local oscillator to generate a carrier signal having a tunable frequency, a first modulator and a power amplifier coupled in cascade to the local oscillator to generate an output signal. The first modulator may be activated from a first modulating signal having a first frequency alternatively defining ON and OFF states of the first modulator. An estimator unit may receive the carrier signal during a time window and detect an estimated frequency variation of the carrier signal during the ON and OFF states. A compensation unit may include a second modulator to generate a compensation signal proportional to the estimated frequency variation and modulated with a second modulating frequency. The second modulating frequency may be substantially the same as the first modulating frequency, and the compensation signal may be added to a bias signal of the local oscillator to tune the tunable frequency.

Oscillator circuits and methods to compensate frequency pulling

There is described a protection apparatus against electrostatic discharges for an integrated circuit; said integrated circuit comprises a radiofrequency or higher frequencies internal circuit. The internal circuit has a first and a second terminals for the output or the input of a radiofrequency or higher frequencies signal. The apparatus comprises first means for electrically connecting said first and second terminals of the internal circuit to at least a PAD and the integrated circuit comprises at least a first and a second supply circuital lines and at least a first and a second protection devices against electrostatic discharges connected to said first and second supply lines. First means have a resistive component and each of said first and second protection devices against the electrostatic discharges have a parasitic capacitive component. The apparatus comprises second means configured to connect said first means and said first and second protection devices against the electrostatic discharges to at least a common circuital point preventing the resistive component of said first means or said internal circuit from combining with the parasitic capacitive components of said first and second protection devices against the electrostatic discharges.

Protection apparatus against electrostatic discharges for an integrated circuit and related integrated circuit

A protection method may prevent a load-mismatch-induced failure in solid-state power amplifiers. In an RF power amplifier, the load voltage standing-wave ratio results in very high voltage peaks at the collector of the final stage and may eventually lead to permanent failure of the power transistor due to avalanche breakdown. The method avoids breakdown by attenuating the input power to the final stage during overvoltage conditions, thus limiting the output collector swing. This is accomplished by a feedback control system, which detects the peak voltage at the output collector node and clamps its value to a given threshold by varying the circuit gain. Indeed, the control loop is unlocked in the nominal condition and it acts when an output mismatching condition is detected. A control circuit also allows a supply-independent collector-clamping threshold to be accurately set.

Protection of output stage transistor of an RF power amplifier

A gain stage control method may include providing a control current signal; generating a regulation current signal connected to the control current signal; transforming the regulation current signal into a biasing current, proportional to the regulation current signal; and biasing the gain stage by using the biasing current. The biasing current may be related to the control current signal by an exponential law.

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Catania, Italy

Angelo Scuderi