Bull Hn Information Systems Italia S.p.a.

Metersit Srl

Angelo Ramolini

Ferruccio Zulian

Carlo Bagnoli

Angelo Lazzari

Andrea Giacosi

A multi-processor system in wherein a plurality of processors have access to a plurality of shared memory modules, comprising a memory control unit, interconnection logic circuits, a system bus for the multipoint connection of the processors to the memory control unit and for the transfer of memory addresses and commands for ordered and successive read/write operations via the system bus and the memory control unit, whilst the transfer of data to and from the memory modules takes place through data channels which connect the various processors on a point-to-point basis to the interconnection logic circuits and via these to a memory data transfer channel.

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Cislago, Italy

Angelo Ramolini