Stmicroelectronics S.r.l.

Sgs-thomson Microelectronics S.r.l.

Angelo Nagari

Pierangelo Confalonieri

Germano Nicollini

Marco Zamprogno

Andrea Baschirotto

Rinaldo Castello

Sergio Pernici

Carlo Pinna

Francesca Girardi

Alessandro Mecchia

Pierangelo Confaloneri

Federico Montecchi

An integrated programmable gain amplifier circuit that receives at an input an analog signal, circuit including an operational amplifier and a gain setup network comprising resistive elements and selection elements, which may be controlled in order to setup the gain of the amplifier circuit. The gain setup network further includes capacitive elements, for defining, together with the resistive elements and the operational amplifier, an anti-aliasing filter of the active RC type.

Integrated programmable gain amplifier circuit and system including the circuit

A single-ended or differential single-stage, or multi-stage sigma-delta analog-to-digital converter includes at least one switched-capacitor integrator comprising a switched-capacitor network receiving as input a signal to be sampled, and an amplifier coupled in cascade to the switched-capacitor network. A circuit is coupled to the amplifier for feeding an analog dither signal to a virtual ground of the amplifier.

Method of adding a dither signal in output to the last integrator of a sigma-delta converter and relative sigma-delta converter

The circuit comprises a first ring oscillator comprising an odd number of inverting elements, a delay element and an output terminal; the delay element responds to a pulse at its input with a predetermined time delay with respect to a predetermined edge of the input pulse and substantially without time delay with respect to the other edge of the input pulse. With a view to avoiding start-up transients and generating pulses with a duty cycle that can be easily modified, the circuit comprises a second ring oscillator, having an output terminal connected to the output terminal of the first oscillator, and a bistable logic circuit having an output terminal connected to the common output of the first and the second oscillator. At least one of the inverting elements of the first oscillator and at least one of the inverting elements of the second oscillator form part of the bistable logic circuit.

Clock-pulse generator circuit

A circuit for selectively converting at least one analog signal into corresponding digital codes. The circuit includes a management block having a plurality of inputs, each adapted for receiving a respective request signal carrying a request to convert the at least one analog signal. The management block is adapted to assign a priority level to the request signals based upon the input where the request signals are received, and is further operative to select one of the request signals based upon the assigned priority level and output a conversion start-up signal corresponding to the selected request signal. The circuit has a conversion block for receiving east one analog signal input and is connected to the management block to receive the conversion start-up signal as input, and start up conversion of the at least one analog signal.

Circuit for selectively analog signals into digital codes

A digital system comprises a digital data processing unit, at least one output buffer connected to the processing unit to generate output signals in response to digital signals arriving from the processing unit and at least one user unit connect as output buffer load. With a view to assuring that the switching current of the output buffer can be set to different values, the output buffer comprises means for fixing the switching current to a value that is substantially constant and independent of the load and means for selectively setting the value of the switching current and the processing unit comprises means for storing a predetermined parameter; said means are connected to the selective setting means for setting the values of the switching current as functions of the predetermined parameter.

Digital system with an output buffer with a switching current settable to load-independent constant values

An A/D converter having capacitors of a first array of sampling capacitors weighted in binary code connected between a first common circuit node and an input terminal to be charged to an input voltage with respect to a ground of a signal to be converted, and in accordance with SAR technique are then selectively connected with two differential reference terminals, and at the same time capacitors of a second array equal to the first and all connected to a second node are selectively connected to ground and the lower differential voltage terminal. The two nodes are connected to the respective inputs of a comparator. A logic unit controls the connections of the capacitors of the two arrays in accordance with a predetermined timing program and as a function of the output of the comparator.

High-speed, high-resolution and low-consumption analog/digital converter with single-ended input

An analog to digital converter includes first and second converter segments having respective first and second arrays of binary weighted capacitors. Each capacitor of the first segment has a first electrode connected to a first common node and a second electrode connected through respective switches to one of a first reference voltage terminal and an input terminal. Each capacitor of the second segment has a first electrode connected to a second common node and a second electrode connected through respective switches to one of the first reference voltage terminal and the input terminal. The converter includes a coupling capacitor connected between the first and second common nodes and capacitance means connected between the first common node and a reference voltage terminal. The coupling capacitor and capacitance means have capacitances, C and C respectively, that substantially satisfy the relationship: (2 &minus;1)&middot;C &minus;C &equals;2 &middot;C, where p is the number of bits coded in the first converter segment and C is the unit capacitance.

High resolution, high speed, low power switched capacitor analog to digital converter

The buffer has an output stage formed by two complementary MOS transistors connected so as to operate in phase opposition between the supply terminals and two driver stages having the input in common. Each driver stage has a first branch comprising a current-generator connected between the gate electrode of the transistor to be driven and a supply terminal and an electronic switch controlled by the input and connected between the same gate electrode and the other supply terminal, and a second branch which comprises, connected in series, a transistor connected as a diode and an electronic switch controlled by the output, and is arranged between the gate electrode of the transistor to be driven and a respective supply terminal. The buffer can control a load with a constant switching current, is simple in structure, and occupies a small area.

Output buffer with constant switching current

A switched capacitor digital-to-analog converter includes a first voltage generator for providing first and second reference voltages, a second voltage generator for providing third and fourth reference voltages selected to match predetermined design values of the first and second reference voltages, and an array of binary weighted capacitors. Each capacitor has a first electrode connected to a common circuit node, which is connected to a converter output terminal and a second electrode selectively connected, through an associated first switching circuit, to either one of the first and second reference voltages or, through an associated second switching circuit, to either one of the third and fourth reference voltages. The converter includes a circuit for monitoring the values of each bit of input digital codes, and a control circuit coupled to the first and second switching circuits to open or close selectively during a bit clock period the connections to the first, second, third, and fourth voltages according to the following criterion: when a bit value of the current input digital code B is equal to the corresponding bit value of the previous input digital code B , the first switching circuit is enabled and the second switching circuit is disabled during the whole bit clock period, and when the monitoring circuit detects a bit value of a current input digital code B to be different from the corresponding bit value of the previous input digital code B , the first switching circuit is disabled and the second switching circuit is enabled during a starting time portion of the bit clock period, while the first switching circuit is enabled and the second switching circuit is disabled during the remaining portion of the bit clock period.

High speed, low power switched-capacitor digital-to-analog converter with a precharge arrangement

A switched capacitor digital to analog converter includes first and second converter segments having respective first and second arrays of binary weighted capacitors. Each capacitor of the first segment has a first electrode connected to a first common node and a second electrode connected through respective switches to one of first and second reference voltage terminals. Each capacitor of the second segment has a first electrode connected to a second common node and a second electrode connected through respective switches to one of the first and second reference voltage terminals. The converter includes a coupling capacitor connected between the first and second common nodes and capacitance means connected between the first common node and a reference voltage terminal. The coupling capacitor and capacitance means have capacitances, C and C respectively, that substantially satisfy the relationship: (2 &minus;1)&middot;C &minus;C &equals;2 &middot;C, where p is the number of bits coded in the first converter segment and C is the unit capacitance.

High resolution, high speed, low power switched capacitor digital to analog converter

A switched capacitor circuit comprising an operational amplifier, having first and second input terminals and an output terminal, the first input terminal being connected to a first reference potential. The operational amplifier is provided with a negative feedback network including a first capacitive element which is connected between the second input terminal and the output terminal of the operational amplifier, a second capacitive element which has a first terminal alternately connected to the second input terminal of the operational amplifier and to a reference potential, and a second terminal connected to a first circuit node which is alternately connected to a signal input terminal and said first output terminal of the operational amplifier. The circuit further includes a third capacitive element connected between the circuit node and a reference potential.

Low distortion circuit with switched capacitors

A set of sampling capacitors weighted according to a binary code is charged through a first capacitive unit, whose capacitance is equal to the sum of the capacitances of the set, at a voltage Vcm&minus;Vin/2. The conversion is carried out by an SAR process by a comparator and a logic unit which operates the switches associated with the capacitors. The final position of the switches is loaded into a register which supplies the digital output signal. To prevent any disturbances in the power supply and reference potential sources from affecting the accuracy of the conversion, two further capacitive units are provided, with the same capacitance as the first capacitive unit. These make it possible to prevent all the disturbances at the input of the comparator in common mode and therefore without any effect on the output.

Analog-digital converter with single-ended input

A second-order double-sampled &Sgr;&Dgr; analog/digital converter uses two fully differential switched-capacitor integrators coupled in cascade. The first integrator has a fully-floating double-sampled, bilinear switched capacitor input structure. The second integrator has a double-sampled lossless discrete integrator (LDI) switched-capacitor input structure. The converter achieves an excellent SNR with a reduced number of switches for low power consumption.

Double-sampled &Sgr;&Dgr; modulator of second order having a semi-bilinear architecture

A .SIGMA..DELTA. digital/analog converter includes a signal reconstructing multirate low pass filter realized as a switched capacitor fully differential, double sampled structure. The input stage of the filter employs only two sampling capacitors, switched alternately on the two inputs of the stage. The input stage further includes two delay circuits (z.sup.-1) in the feed line of the bitstream towards one of the two inputs of the multistage SC filter. The zeroes introduced in the transfer function reduce the noise energy in the vicinity of frequencies f.sub.s /2.sup.n, preserving the SNR even with a relatively large mismatch between the capacitors.

Double sampled switched capacitor low pass multirate filter for a

In a switched operational amplifier including a differential input stage and at least a second output stage, the compensation capacitor commonly required to couple the output node of the second stage with the respective output node of the input differential stage of the amplifier is associated with a switching circuit. The switching circuit is controlled by the same control phase that enables/disables the amplifier for interrupting the connection between the compensation capacitor (CC) and the output node of the differential input stage during a phase in which the amplifier is disabled for reducing the switch-on time. Notably the differential input stage of the operational amplifier remains always active and only the second output stage is switched on and off.

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Cilavegna, Italy

Angelo Nagari