Stmicroelectronics S.r.l.

Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno

Other

Sgs-thomson Microelectronics S.r.l.

Sgs-thomas Microelectronics S.r.l.

Angelo Magri

Ferruccio Frisina

Giuseppe Ferla

Leonardo Fragapane

Antonino Alessandria

Richard A Blanchard

Stefania Fortuna

Mario Giuseppe Saggio

Agatino Minotti

Antonio Giuseppe Grimaldi

Cateno Marco Camalleri

Giuseppe Arena

Maurizio Maria Ferrara

Giacomo Barletta

Gaetano Bazzano

Caterina Donato

Ferrucio Frisina

Antonio Pinto

An electronic device is integrated on a chip of semiconductor material having a main surface and a substrate region with a first type of conductivity. The electronic device has a vertical MOS transistor, formed in an active area having a body region with a second conductivity type. A set of one or more cells each one having a source region of the first conductivity, a gate region of electrically conductive material in a gate trench extending from the main surface in the body region and in the substrate region, and an insulating gate layer, and a termination structure with a plurality of termination rings surrounding at least part of the active area on the main surface, each termination ring having a floating element of electrically insulating material in the termination trench extending from the main surface in the chip and at least one bottom region of said semiconductor material of the second conductivity type extending from at least one deepest portion of a surface of the termination trench in the chip; the termination trenches have a depth from the main surface decreasing moving away from the active area.

Electronic device of vertical MOS type with termination trenches having variable depth

A power device integrated on a semiconductor substrate and having a plurality of conductive bridges within a trench gate structure. In an embodiment, a semiconductor substrate includes a trench having sidewalls and a bottom, the walls and bottom are covered with a first insulating coating layer which then also includes a conductive gate structure. An embodiment provides the formation of the conductive gate structure with covering at least the sidewalls with a second conductive coating layer of a first conductive material. This results in a conductive central region of a second conductive material having a different resistivity than the first conductive material forming a plurality of conductive bridges between said second conductive coating layer and said conductive central region.

Integrated power device on a semiconductor substrate having an improved trench gate structure

An embodiment of a method for manufacturing a power device with conductive gate structures inside etched trenches. Such trenches include sidewalls and a bottom, wherein covering the sidewalls and the bottom of the trench is a first insulating coating layer. In the formation of the conductive gate structure, openings within the first material in the trench are made such that a conductive central region of a second conductive material having a different resistivity than the first conductive material are able to be electrically coupled together through a plurality of conductive bridges between said second conductive coating layer and said conductive central region.

Method for manufacturing an integrated power device having gate structures within trenches

Power MOS device of the type comprising a plurality of elementary power MOS transistors having respective gate structures and comprising a gate oxide with double thickness having a thick central part and lateral portions of reduced thickness. Such device exhibiting gate structures comprising first gate conductive portions overlapped onto said lateral portions of reduced thickness to define, for the elementary MOS transistors, the gate electrodes, as well as a conductive structure or mesh. Such conductive structure comprising a plurality of second conductive portions overlapped onto the thick central part of gate oxide and interconnected to each other and to the first gate conductive portions by means of a plurality of conducive bridges.

Power MOS electronic device and corresponding realizing method

A trench is formed in a semiconductor body, the side walls and the bottom of the trench covered with a first dielectric material layer, the trench filled with a second dielectric material layer, the first and the second dielectric material layers are etched via a partial, simultaneous, and controlled etching such that the dielectric materials have similar etching rates, a gate-oxide layer having a thickness smaller than the first dielectric material layer deposited on the walls of the trench, a gate region of conductive material formed within the trench, and body regions and source regions formed within the semiconductor body at the sides of and insulated from the gate region. Thereby, the gate region extends only on top of the remaining portions of the first and second dielectric material layers.

Method of manufacturing a semiconductor power device

A method for manufacturing electronic devices on a semiconductor substrate with wide band gap that includes the steps of: forming a screening structure on the semiconductor substrate to include at least a dielectric layer that leaves a plurality of areas of the semiconductor substrate exposed, carrying out at least a ion implantation of a first type of dopant in the semiconductor substrate to form at least a first implanted region, carrying out at least a ion implantation of a second type of dopant in the semiconductor substrate to form at least a second implanted region inside the at least a first implanted region, carrying out an activation thermal process of the first type and second type of dopant with low thermal temperature suitable to complete the formation of the at least first and second implanted regions without diffusing the at least first and at least second type dopants in the substrate.

Method for manufacturing electronic devices integrated in a semiconductor substrate and corresponding devices

Power electronic MOS device of the type comprising a plurality of elementary power MOS transistors and a gate structure comprising a plurality of conductive strips realized with a first conductive material such as polysilicon, a plurality of gate fingers or metallic tracks connected to a gate pad and at least a connection layer arranged in series to at least one of said conductive strip. Such gate structure comprising at least a plurality of independent islands formed on the upper surface of the conductive strips and suitably formed on the connection layers. Said islands being realized with at least one second conductive material such as silicide.

Switching-controlled power MOS electronic device

A vertical conduction power electronic device package and corresponding assembly method comprising at least a metal frame suitable to house at least a plate or first semiconductor die having at least a first and a second conduction terminal on respective opposed sides of the first die. The first conduction terminal being in contact with said metal frame and comprising at least an intermediate frame arranged in contact with said second conduction terminal.

Vertical conduction power electronic device package and corresponding assembling method

A semiconductor power device includes an insulated gate and a trench-gate structure. The trench-gate structure is formed on a semiconductor substrate covered by an epitaxial layer. The trench is formed in the semiconductor to form the device gate region. A dielectric coating is provided on the inner and bottom walls of the trench. The gate region includes a conductive spacer layer on the coating layer only on the inner walls of the trench.

Semiconductor power device with insulated gate and trench-gate structure and corresponding manufacturing method

An electronic power device of improved structure is fabricated with MOS technology to have a gate finger region and corresponding source regions on either sides of the gate region. This device has a first-level metal layer arranged to independently contact the gate region and source regions, and has a protective passivation layer arranged to cover the gate region. Advantageously, a wettable metal layer, deposited onto the passivation layer and the first-level metal layer, overlies said source regions. In this way, the additional wettable metal layer is made to act as a second-level metal.

Method for enhancing the electric connection between a power electronic device and its package

A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulating material layer placed above the semiconductor material layer, a conductive material layer placed above the first insulating material layer, and a second insulating material layer placed above the conductive material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes an elongated window in the insulated gate layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided. The MOS technology power device further includes a plurality of insulating material sidewall spacers disposed above the semiconductor material layer along elongated edges of each elongated window to seal the edges of each elongated window in the insulated gate layer from a source metal layer disposed over the insulated gate layer and the semiconductor material layer. The source metal layer contacts each body region and each source region through each elongated window along the length of the elongated body region.

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Belpasso, Italy

Angelo Magri