Bull Hn Information Systems Italia S.p.a.

Bull S.a.

Angelo Lazzari

Carlo Bagnoli

Ferruccio Zulian

Angelo Casamatta

Marco Gianellini

Angelo Ramolini

Dynamic random access memory (DRAM) having variable configuration for data processing system and corresponding expansion support for the interleaved-block configuration thereof

A multi-processor system in wherein a plurality of processors have access to a plurality of shared memory modules, comprising a memory control unit, interconnection logic circuits, a system bus for the multipoint connection of the processors to the memory control unit and for the transfer of memory addresses and commands for ordered and successive read/write operations via the system bus and the memory control unit, whilst the transfer of data to and from the memory modules takes place through data channels which connect the various processors on a point-to-point basis to the interconnection logic circuits and via these to a memory data transfer channel.

Multi-processor system with shared memory

A multiprocessor system having global data replicated in all local memories, each local memory related to one of the system central processing units (CPUs), where consistency of the global data in each of the local memories is provided by a global write procedure according to which an agent CPUZ, willing to modify a global data in its own local memory, issues a write command on the system bus for performing the write operation in the local memory of another destination CPU of the system and characterizes the write command as a global write, so that all the CPUs connected to the system bus (including CPUZ) detect such command, perform such write operation in their related local memory and provide the destination CPU with a signal indicative of a performed write operation, so that the destination CPU, as 'replier', may signal to CPUZ the successful execution of the global write. By this procedure, it is possible to use standard, commercially available system bus and interface circuits which require, for correct execution of the system bus protocol, the activation of both an 'agent' or requesting processor and a 'replier' or destination processor.

Multiprocessor system having global data replication

Growing community of inventors

Vigevano, Italy

Angelo Lazzari