Stmicroelectronics S.r.l.

Maxtor Corporation

Angelo Dati

Davide Giovenzana

Augusto Andrea Rossi

Giorgio Betti

Danilo Pietro Pau

Viviana D'Alto

Filippo Brenna

Filippo Santinello

Maurizio Zuffada

Melchiorre Bruccoleri

Kelly K Fitzpatrick

Antonio Fincato

Ivan Bietti

Bahjat Zafer

Pierandrea Savo

Salvatore Mario Rotolo

John J McEwen, Legal Representative

Luca Reggiani

Ezio Iacazio

A system for detecting objects, for driver assistance equipment in motor vehicles for example, includes a transmitter for transmitting towards an object an optical signal having a signal energy. The optical signal transmitted includes at least one encoded pulse sequence with the signal energy distributed over the pulse sequence. A receiver receives an echo signal resulting from reflection of the optical signal at the object with the time delay of the echo signal is indicative of the distance to the object.

Method of detecting objects, corresponding system and apparatus

A method of storing a data file, particularly in the MPEG format and including a flow of different frames, comprises a protection system for the data file based on a parameter stored in the data file. Advantageously, the storage method comprises selectively protecting the frames by storing parameters that are associated with corresponding different frames whose values are selected to provide a playing quality level requested by an end user. Also, a method is provided for decoding a data file, particularly of the MPEG type and including a flow of different frames, wherein the data file is stored per above.

Data-file storage, particularly for MPEG format files

The method and architecture improve the robustness of a synchronization system through a minimum latency loop, for Hard Disk Drives (HDD), for example, wherein synchronous detection processing is performed for timing recovering of a correct sampling phase and frequency and by a first acquisition step of a known preamble signal pattern, for generating a timing periodic signal, followed by a second tracking step, for recovering phase, frequency and gain sampling errors of the synchronization signal including a header followed by an unknown data content. Advantageously, a feedback loop including a numeric preamble generator (NPG) is provided for obtaining a reduced latency in the acquisition phase. The NPG stores preamble values for different phase offset.

Method for using a minimum latency loop for a synchronization system in a hard disk drive

A method for detecting signals affected by intersymbol interference provides for a path memory in the form of a trellis admitting survivor paths comprising a first and a second stage. The first stage includes a shift register exchange with a given number of states and a given length &#x3bb;. The first stage outputs a first state Son the survivor path for the best state A, and a second state Son the survivor path for another state B. The second stage is configured as a two-state shift register exchange having a respective memory length &#x39b;, including respective first and second registers. In the respective first and second registers the survivor paths are stored leading to a respective first &#x3c3;and second &#x3c3;state, whereby the respective first register contains the backend of the best survivor path, while the respective second register contains the backend of an alternative survivor path.

Trellis-based detection process and system

A receiver in a data read channel has an input terminal for receiving an input signal provided by a transmitter of the data read channel, and produces an output signal at an output terminal. The receiver includes a finite impulse response (FIR) filter coupled to the input terminal and having filter coefficients capable of being adapted, an interpolated timing-recovery circuit coupled to an output of the FIR filter, the timing-recovery circuit having an output signal coupled to the output terminal of the receiver, and a timer circuit coupled to the output terminal and feedback connected to the timing-recovery circuit, wherein the coefficients of the timing-recovery circuit are dynamically adapted using a cost weighted function through a signal power spectrum of the data read channel.

Equalization and interpolated timing recovery for a partial response channel

A method for storing user data on a hard disk drive system comprises distributing user data across a plurality of independent data sectors, with each data sector including a first header having a first preamble field and a first sync mark field, and a second header having a second preamble field and a second sync mark field. The method performs a first timing recovery phase for recovering signal amplitude by acquiring phase and frequency lock from at least one of the preamble fields, and performs a subsequent frame synchronous detection phase by acquiring a corresponding sync mark field.

Method to improve data reliability on hard disk drive systems

In the MSN encoded form, the symbols of each block of the present invention define a running digital sum (RDS) value, defined as RDS([aa. . . a])=&#x2212;&#x3a3;(&#x2212;1)where the symbols abelong to the set {} and the sum extends for values of i from 0 to N&#x2212;1. An encoder is configured to satisfy at least one of the following characteristics: a) blocks of symbols with a given length (L) are used for encoding, wherein RDS=RDS+4.K, where K is an integer, RDS is the said running digital sum, RDSis defined as zero for even values of the said length (L), and one for odd values of said length (L), and b) blocks of symbols with a given length (L) are used for MSN coding and encoding is effected by selecting encoded blocks such that the set of running digital sum (RDS) values is the set with the minimum number of elements that satisfy the required rate value, defined as the ratio between the length of the input blocks and the length of the output blocks. A decoder with a simplified trellis structure is used for decoding (as in decoding a digital signal read from media on which the signal in question has been recorded via a vertical or perpendicular magnetic recording technique, for example).

Shaped spectral coding and recording systems therefor

A system for decoding digital signals subjected to block coding includes a post-processor that corrects the codewords affected by error, identifying them with the most likely sequence that is a channel sequence and that satisfies a syndrome check. The post-processor is a finite-state machine described by a graph that represents the set of error events. The post-processor evolves in steps through subsequent transition matrices, deleting at each step the paths that accumulate an invalid number of error events or an excessive number of wrong bits, paths that accumulate a total reliability higher than a given threshold, paths with an invalid check on the received sequence, and paths that reveal an invalid syndrome after having reached a maximum number of events.

Process for decoding signals and system and computer program product therefore

A system provides two distinct solutions for encoding and decoding servo positioning data for a hard disk drive. A first solution includes: encoding each group of four bits of a pattern signal in a Matched Spectral Null (MSN) format through an intermediate rate 4/6 code; providing a duplicated bit for each bit of the six bit code word obtained with the previous step. A second solution includes: encoding each group of four bit of the pattern signal adding a parity check bit as an intermediate rate &#x2158; code; encoding each of the five bits using the biphase map. Both solutions include subsequently: reading a servo wedge information signal using a read and write channel of the hard disk drive; and using a trellis Partial Response decoding scheme matched to the encoded word for obtaining angular and radial information for the head positioning.

Encoding and decoding process and corresponding data detector

A control signal compensation method is particularly intended for an analog/digital processing system provided with a control loop, including in turn a controller and a monitoring circuit. The method includes storing corrections made by the controller, fast processing such as corrections before transmitting the corrections throughout the control loop, and generating a compensation signal for the latency effects of the controller, by the use of a negative feedback loop provided at the monitoring circuit level. A compensation control system implements the above method, and an analog/digital processing system incorporates such a compensation control system

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Abbiategrasso, Italy

Angelo Dati