Bull Hn Information Systems Italia S.p.a.

Angelo Casamatta

Calogero Mantellina

Daniele Zanzottera

Carlo Bagnoli

Angelo Lazzari

A data-processing system with cc-NUMA architecture including a plurality of nodes each constituted by at least one processor intercommunicating with a DRAM-technology local memory using a local bus, the nodes intercommunicating using remote interface bridges and at least one intercommunication ring. The at least one processor has access to a system memory space defined by memory addresses. Each node includes a unit for configuring the local memory, for uniquely mapping a first portion of the system memory space, which is different for each node, onto a portion of the local memory and for mapping the portion of the system memory space which as a whole is uniquely mapped onto a portion of the local memory of all the other nodes onto the remaining portion of the local memory, and a SRAM-technology memory for storing labels with associated with a block of data stored in the remaining portion of local memory and each comprising an index identifying the block and bits indicating a coherence state of the block so that the remaining portion of local memory in each node constitutes a remote cache of the node.

Data-processing system with CC-NUMA (cache-coherent, non-uniform memory access) architecture and remote cache incorporated in local memory

Interface bridge (,) between a system bus (ASBUS) and at least one local bus (,), the system space directly addressable through said system bus being greater than the system space directly addressable through the local bus, comprising a plurality of programmable decoders (,) each of which defines a distinct range within the range directly addressable through the local bus, and a range attribute as range of local bus addresses to be translated or to be transferred directly to the system bus and also identifies a local bus address as being included or otherwise within the range, so that depending on whether the local bus address belongs to one of the ranges or not and on the range attribute, the local bus address is transferred to the system bus as a direct address or as an address translated by a translation logic (,) and capable of addressing the entire system space.

Interface bridge between a system bus and local buses with translation of local addresses for system space access programmable by address space

In a multiprocessor system having global data replication in each of the local memories, each associated with one of the processors, the global data allocation in the several local memories is performed by translating global data logical addresses into addresses conventionally defined as real, the translation being performed by a first translation unit associated with and managed by the processor which generates the global data. The first translation is followed by the translation of the real address into a physical address generally differing for each local memory and performed by a plurality of translation units, each associated with one of the local memories and managed by the processor associated with that local memory.

Multiprocessor system with global data replication and two levels of

A multiprocessor system having global data replicated in all local memories, each local memory related to one of the system central processing units (CPUs), where consistency of the global data in each of the local memories is provided by a global write procedure according to which an agent CPUZ, willing to modify a global data in its own local memory, issues a write command on the system bus for performing the write operation in the local memory of another destination CPU of the system and characterizes the write command as a global write, so that all the CPUs connected to the system bus (including CPUZ) detect such command, perform such write operation in their related local memory and provide the destination CPU with a signal indicative of a performed write operation, so that the destination CPU, as 'replier', may signal to CPUZ the successful execution of the global write. By this procedure, it is possible to use standard, commercially available system bus and interface circuits which require, for correct execution of the system bus protocol, the activation of both an 'agent' or requesting processor and a 'replier' or destination processor.

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Milan, Italy

Angelo Casamatta