Stmicroelectronics S.r.l.

Micron Technology Incorporated

Other

Hynix Semiconductor Inc.

Angelo Bovino

Rino Micheloni

Roberto Ravasio

Vincenzo Altieri

Luca Crippa

Chiara Missiroli

Mario De Matteis

A multi-level flash memory device allows for a faster and more effective configuration of the operating parameters of the memory device for performing the different functioning algorithms of the memory. The identification of an optimal configuration of the operating parameters of the memory device during testing is simplified by allowing for a one-time processing of configuration bits into algorithm-friendly data that are stored in an embedded ancillary random access memory at every power-on of the memory device. This is done by executing a specific power-on algorithm code stored in the ancillary read only memory of the embedded microprocessor.

Configuration of a multilevel flash memory device

A multi-level flash memory device allows for a faster and more effective configuration of the operating parameters of the memory device for performing the different functioning algorithms of the memory The identification of an optimal configuration of the operating parameters of the memory device during testing is simplified by allowing for a one-time processing of configuration bits into algorithm-friendly data that are stored in an embedded ancillary random access memory at every power-on of the memory device This is done by executing a specific power-on algorithm code stored in the ancillary read only memory of the embedded microprocessor.

Configuration of a multi-level flash memory device

A memory has one bus for data, addresses, and commands. A data register is coupled to the bus to store the data written to and read from the memory, a command register is coupled to the bus for receiving memory commands, and an address register is coupled to the bus to address the memory. The memory also includes an Error Correction Code circuit for calculating an ECC. The memory is configured to be responsive to external commands for controlling the operation of the ECC circuit for reading or writing of the ECC that are separate from external commands controlling reads or writes of the memory data. The memory may also include a status register that stores information regarding the passing or failing of the ECC.

Memory with embedded error correction codes

Multi-level programming allows for writing a first and a second bit in selected cells by separately programming the first bit from the second bit. Programming of the first bit determines a shifting from a first threshold level to a second threshold level. Programming of the second bit requires a preliminary reading to detect whether the first bit has been modified, performing a first writing step to bring the cell to a third threshold voltage if the first bit has been modified and performing a second writing step to bring the selected cell to a fourth threshold voltage different from the third threshold level if the first bit has not been modified. For increasing reading and program reliability, during preliminary reading of the second portion a reading result is forced to correspond to the first threshold level.

Method for accessing a multilevel nonvolatile memory device of the flash NAND type

A non-volatile memory device is proposed. The non-volatile memory device includes a plurality of memory cells each one having a programmable threshold voltage, and means for reading a set of selected memory cells with respect to a plurality of reference voltages, for each selected memory cell the means for reading including means for charging a reading node associated with the selected memory cell with a charging voltage, means for biasing the selected memory cell with a biasing voltage, means for connecting the charged reading node with the biased selected memory cell, and means for sensing a voltage at the reading node after a predefined delay from the connection, for at least a first one of the reference voltages the biasing voltage being a first biasing voltage equal to the first reference voltage and the delay being a common first delay, wherein for at least a second one of the reference voltages the biasing voltage is a second biasing voltage different from the second reference voltage, and the delay is a second delay different from the first delay.

NAND flash memory with erase verify based on shorter evaluation time

A page buffer for an electrically programmable memory including at least one read/program unit having a coupling line operatively associable with at least one of said bit lines and adapted to at least temporarily storing data bits read from or to be written into either one of the first or second memory page stored in the memory cells of a selected memory cell sets. The read/program unit includes enabling means for selectively enabling a change in programming state of a selected memory cell by causing the coupling line to take one among a program enabling potential and a program inhibition potential, conditioned to a target data value to be stored in the first group of data bits of the selected memory cell and an existing data value already stored in the second group of data bits of the selected memory cell. The enabling means includes reading means for retrieving the existing data value, means for receiving an indication of the target data value, combining means for combining the received target data value with the retrieved existing data value, thereby modifying said indication of the target data value so as to obtain a modified indication. Conditioning means in the combining means condition a potential of the coupling line based on the existing data value and the modified indication so as to cause the coupling line to take the program enabling potential or the program inhibition potential.

Growing community of inventors

Brunico, Italy

Angelo Bovino