Advanced Micro Devices Corporation

Spansion Llc.

Other

Cypress Semiconductor Corporation

Globalfoundries Inc.

Infineon Technologies LLC

Fasl LLC

Fujitsu Corporation

Fujitsu Amd Semiconductor Limited

Angela Tai Hui

Minh Van Ngo

Mark T Ramsbey

Mark S Chang

Yu Nan Sun

Ning Cheng

Kuo-Tung Chang

Tuan Duc Pham

Wenmei Li

Scott Allan Bell

Shenqing Fang

Hiroyuki Kinoshita

Chi K Chang

Unsoon Kim

Lei Xue

Kouros Ghandehari

Fei Wang

Jihwan Choi

Jusuke Ogura

Bhanwar Singh

Sameer S Haddad

Yider Wu

Hirokazu Tokuno

Hiroyuki Ogawa

Jeffrey Allan Shields

Hidehiko Shiraiwa

Jean Y Yang

Tazrien Kamal

Ramkumar Subramanian

Dawn M Hopper

Simon S Chan

Huaqiang Wu

Hiro Kinoshita

Paul Raymond Besser

Christopher F Lyons

Sergey D Lopatin

Suzette Keefe Pangrle

Chun Chen

Kashmir S Sahota

Amol Ramesh Joshi

Hung-Sheng Chen

Jaeyong Park

Calvin T Gabriel

Richard J Huang

Chih-Yuh Yang

Alexander H Nickel

Robert A Huertas

Tatsuya Kajita

Minh-Van Ngo

Cinti Xiaohua Chen

Matthew S Buynoski

Robin W Cheung

Lu You

Mark W Randolph

Arvind Halliyal

Timothy J Thurgate

Chungho Lee

Harpreet Kaur Sachar

Emmanuil Lingunis

Patrick K Cheung

Steven C Avanzino

Yowjuang William Liu

Michael K Templeton

Marina V Plat

Nicholas H Tripsas

Yue-Song He

Uzodinma Okoroanyanwu

Wenge Yang

Hamid Partovi

Simon Siu-Sing Chan

Susan H Chen

Chun Jiang

Jeff P Erhardt

Pei-Yuan Gao

James J Xie

James K Kai

Ming-Ren Lin

Richard M Fastow

Subhash Gupta

Kazuhiro Kurihara

John JianShi Wang

William George En

Hao Fang

Narbeh Derhacobian

Yi He

Wei Zheng

Ravi S Sunkavalli

Robert B Ogle

Ankur Agarwal

Lewis N Shen

Rinji Sugino

Krishnashree Achuthan

Ashot Melik-Martirosian

YongZhong Hu

Jean Yee-Mei Yang

Inkuk Kang

James Jiahua Yu

Jayendra D Bhakta

Maria Chow Chan

Weidong Qian

Disclosed herein is a semiconductor device comprising a first dielectric disposed over a channel region of a transistor formed in a substrate and a gate disposed over the first dielectric. The semiconductor device further includes a second dielectric disposed vertically, substantially perpendicular to the substrate, at an edge of the gate, and a spacer disposed proximate to the second dielectric. The spacer includes a cross-section with a perimeter that includes a top curved portion and a vertical portion substantially perpendicular to the substrate. The perimeter further includes a discontinuity at an interface of the top curved portion with the vertical portion. Further, disclosed herein are methods associated with the fabrication of the aforementioned semiconductor device.

Method of spacer formation with straight sidewall of memory cells

In an example embodiment, a method comprises: forming first spacers adjacent to a memory cell formed on a substrate, each of the first spacers being formed in direct contact with the substrate, where forming the memory cell includes forming a control gate electrode and a tunnel oxide layer over the substrate and subsequently etching completely at least the control gate electrode and the tunnel oxide layer that are disposed beyond the memory cell; forming an interlayer dielectric layer over the memory cell and the first spacers; forming a contact hole through the interlayer dielectric layer to at least reach the substrate; subsequent to forming the contact hole, forming a second spacer adjacent to one of the first spacers, where a height of the second spacer is greater than a height of the first spacers, the second spacer substantially contacting the substrate and the interlayer dielectric layer; and forming a contact in the contact hole.

Contacts for semiconductor devices

A semiconductor device having a substrate, a dielectric layer over the substrate, a first gate conductor, an inter-gate dielectric structure and a second gate conductor is disclosed. A gate dielectric structure is disposed between the first gate conductor and the dielectric layer, and may include two or more dielectric films disposed in an alternating manner. The inter-gate dielectric structure may be disposed between the first gate conductor and the second gate conductor, and may include two or more dielectric films disposed in an alternating manner. The second gate conductor is formed in an L shape such that the second gate has a relatively low aspect ratio, which allows for a reduction in spacing between adjacent gates, while maintaining the required electrical isolation between the gates and contacts that may subsequently be formed.

Split-gate semiconductor device with L-shaped gate

A memory device includes a number of memory cells and a dielectric layer formed over the memory cells. The memory device also includes contacts formed in the dielectric layer and spacers formed adjacent the side surfaces of the contacts. The spacers may inhibit leakage currents from the contacts.

Methods and apparatus for manufacturing semiconductor devices, and such semiconductor devices, are described. According to various aspects of the disclosure, a semiconductor device comprises a first region, a second region, a first polysilicon region, and a second polysilicon region. The first polysilicon region is formed over the first and second regions of the semiconductor device. Portions of the first and polysilicon layers that are uncovered by either of a first mask and a second mask are removed. The first mask is formed on the first polysilicon layer and the second mask is formed on the second polysilicon layer in the first region and not on in the second region.

Buried hard mask for embedded semiconductor device patterning

Spacer formation with straight sidewall

Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.

HTO offset for long leffective, better device performance

An integrated circuit comprises a first poly-silicon region including a first poly-silicon layer, a second poly-silicon layer disposed over the first poly-silicon layer, a first poly-silicon finger associated with the first poly-silicon layer, and a second poly-silicon finger associated with the second poly-silicon layer. The first poly-silicon finger and the second poly-silicon finger are oriented in a substantially orthogonal manner relative to each other. The integrated circuit comprises a second poly-silicon gate region including the first poly-silicon layer. The first polysilicon gate region and the second polysilicon gate region each have different poly-silicon gate structures.

Integrating transistors with different poly-silicon heights on the same die

Methods and apparatus for manufacturing semiconductor devices, and such semiconductor devices, are described. According to various aspects of the disclosure, a semiconductor device can be manufactured by forming a core region of the semiconductor device and forming a periphery region of the semiconductor device. A first polysilicon region can then be formed over the core and periphery regions of the semiconductor device. A first mask is formed on the first poly silicon layer and a second polysilicon layer is disposed such that the second polysilicon layer covers the first mask. A second mask can then be formed on the second polysilicon layer. After forming the second mask, portions of the first and second polysilicon layers that are uncovered by either the first or second masks are removed.

Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the semiconductor substrate, the memory device can improve the electrical isolation between memory cells, thereby preventing and/or mitigating TPD.

Oro and orpro with bit line trench to suppress transport program disturb

During formation of a charge trap separation in a semiconductor device, a polymer deposition is formed in a reactor using a first chemistry. In a following step, a second chemistry can be used to etch the polymer deposition in the reactor. The same or similar second chemistry can be used in a second etching step to expose a first oxide layer in each of the cells of the semiconductor device and to form a flat upper surface. This additional etch step can also be performed by the reactor, thereby reducing the number of machines required in the formation process.

Forming charge trap separation in a flash memory semiconductor device

Charge-trapping field effect transistors may be formed into an array on a wafer suitable to be a NAND memory device. A thick oxide layer is applied over the gates to ensure that the gap between the gates is filled. The filled gap substantially prevents nitride from being trapped, which could otherwise decrease the yield of the devices. This technique, and its variations, are useful for a range of semiconductor devices.

Spacer design to prevent trapped electrons

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Fremont, CA, United States of America

Angela Tai Hui