Intel Corporation

Angela D Schmid

Jason W Brandt

Ahmad Yasin

Michael W Chynoweth

Matthew C Merten

Seth Abraham

Kimberly C Weier

Beeman C Strong

Andreas Kleen

Stanislav Viktorovich Bratanov

Grant G Zhou

Ofer Levy

Jonathan D Combs

Charlie J Hewett

A processor is to execute and retire instructions for a virtual machine. A reload register is coupled to the core is to store a reload value. A performance monitoring counter (PMC) register is coupled to the reload register and an event-based sampler operatively is coupled to the reload register and the PMC register. The event-based sampler includes circuitry to load the reload value into the PMC register and increment the PMC register after detecting each occurrence of an event of a certain type as a result of execution of the instructions. Upon detecting an occurrence of the event after the PMC register reaches a predetermined trigger value, the event-based sampler is to execute microcode to generate field data for elements within a sampling record, wherein the field data relates to a current processor state of execution, and reload the reload value from the reload register into the PMC register.

Virtualizing precise event based sampling

A core includes a memory buffer and executes an instruction within a virtual machine. A processor tracer captures trace data and formats the trace data as trace data packets. An event-based sampler generates field data for a sampling record in response to occurrence of an event of a certain type as a result of execution of the instruction. The processor tracer, upon receipt of the field data: formats the field data into elements of the sampling record as a group of record packets; inserts the group of record packets between the trace data packets as a combined packet stream; and stores the combined packet stream in the memory buffer as a series of output pages. The core, when in guest profiling mode, executes a virtual machine monitor to map output pages of the memory buffer to host physical pages of main memory using multilevel page tables.

A processing device implementing an elapsed cycle timer in last branch records (LBRs) is disclosed. A processing device of the disclosure includes a last branch record (LBR) counter to iterate with each cycle of the processing device. The processing device further includes at least one register communicably coupled to the LBR counter, the at least one register to provide an LBR structure comprising a plurality of LBR entries. An LBR entry of the plurality of LBR entries includes an address instruction pointer (IP) of a branch instruction executed by the processing device, an address IP of a target of the branch instruction, and an elapsed time field that stores a value of the LBR counter in response to creation of the LBR entry.

Elapsed cycle timer in last branch records

A processor and method are described for implementing performance monitoring using a fixed function performance counter. For example, one embodiment of an apparatus comprises: a fixed function performance counter to decrement or increment upon occurrence of an event in the processing device; a precise event based sampling (PEBS) enable control communicably coupled to the fixed function performance counter; a PEBS handler to generate and store a PEBS record comprising architectural metadata defining a state of the processing device at a time of generation of the PEBS record; and a non-precise event based sampling (NPEBS) module communicably coupled to the PEBS enable control and the PEBS handler, the NPEBS module to cause the PEBS handler to generate the PEBS record for the event upon the fixed function performance counter reaching a specified value.

Method and apparatus for processor performance monitoring

A processing device implementing an elapsed cycle timer in last branch records (LBRs) is disclosed. A processing device of the disclosure includes a last branch record (LBR) counter to iterate with each cycle of the processing device and an LBR structure communicably coupled to the LBR counter. The LBR structure comprises a plurality of LBR entries. Furthermore, an LBR entry of the plurality of LBR entries comprises an address instruction pointer (IP) of a branch instruction executed by the processing device, an address IP of a target of the branch instruction, and an elapsed time field that stores a value of the LBR counter when the LBR entry is created.

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Pleasanton, CA, United States of America

Angela D Schmid