Marvell International Limited

Qlogic Corporation

Angel G Perozo

William W Dennin, Iii

Theodore Curt White

Aurelio J Cruz

Apparatus having corresponding methods and computer-readable media comprise: a memory having a plurality of ports; a plurality of processors, wherein each processor is configured to access a respective port of the memory, and wherein each processor is configured to wait responsive to assertion of a respective wait signal; and an arbiter configured to assert the wait signals responsive to memory enable signals asserted by the processors such that the memory is accessed by only one of the processors at a time.

Sharing memory using processor wait states

A method and system for processing data by a storage controller with a buffer controller coupled to a buffer memory is provided. The method includes, evaluating incoming data block size; determining if the incoming data requires padding; and padding incoming data such that the incoming data can be processed by the buffer controller. The method also includes determining if any pads need to be removed from data that is read from the buffer memory; and removing pads from the data read from the buffer memory. The buffer controller can be set in a mode to receive any MOD size data and includes a first channel with a FIFO for receiving incoming data via a first interface. The buffer controller mode for receiving incoming data can be set by firmware.

System and method for transferring data in storage controllers

A storage controller includes a memory controller that interfaces with memory that stores data. A first receive logic interface provides an interface to a host. A second receive logic interface provides an interface to a storage device. A power save module has a power save mode in which at least a clock of the memory controller is turned off while a clock for operating the first receive logic interface and the second receive logic interface is kept on.

Power save module for storage controllers

A storage drive system including an interface and a channel. The interface is configured to i) receive frames from a host and ii) process the frames. The channel is configured to i) receive the frames from the interface and ii) transfer the frames from the interface to a buffer memory. The channel includes a first register configured to store bit values corresponding to frame processing, and includes a first module configured to i) detect frame types of the frames and ii) in response to detecting a first frame type, stop receiving a second frame type while selectively continuing to receive a third frame type based on the bit values.

Method and system for processing frames in storage controllers

A controller for interfacing a host and storage device is provided. The controller includes a channel that can receive data from the storage device in a first format and store the data in an intermediate buffer memory in a second format. The channel includes conversion logic that converts data from the first format to the second format and from the second format to the first format depending upon whether data is being read or written from the buffer memory. The conversion logic uses a shuttle register and shuttle counter for aligning data that is being transferred between the storage device and the buffer memory by appropriately concatenating data to meet the first and second format requirements. The first format is based on 10-bit symbols and the second format is based on 8-bits.

System and method for reading and writing data using storage controllers

A hard disk controller includes a direct access module. The direct access module is configured to receive a data stream from a host, the data stream including a plurality of data words to be transferred to a storage device, generate data integrity information based on the plurality of data words, insert the data integrity information into the data stream prior to transmitting the data stream to a buffer memory, and transmit the data stream. A buffer control module is configured to receive the data stream including the data integrity information from the direct access module, and store the data stream in the buffer memory.

System and method for error correction

Method and system for transferring data between a computing system and a storage device is provided. The system includes a storage controller including a frame snooper module that detects a TMR and generates a pause signal to a channel that stops the channel from sending any non-data frames to a buffer memory, wherein the channel continues to receive and process data frames while the channel is stopped from sending the command frames to the buffer memory; a counter for counting TMRs; and logic for generating an interrupt if a number of TMRs received exceeds a certain threshold value. The method includes detecting a TMR generating a command to stop a channel from receiving non-data frames while continuing to receive data frames from a Fiber Channel interface; and generating an interrupt to a processor after a certain number of TMRs are received.

An error correction system for a data storage device comprises a direct access module and a buffer control module. The direct access module receives a data stream that includes a plurality of data words from a host, generates data integrity information based on the plurality of data words, and inserts the data integrity information into the data stream. The buffer control module receives the data stream and stores the data stream to a memory.

A method and system using a storage controller for transferring data between a storage device and a host system is provided. The storage controller includes, a power save module that is enabled in a power save mode after a receive logic in the storage controller has processed all frames and during the power save mode at least a clock is turned off to save power while a clock for operating the receive logic is kept on to process any unsolicited frames that may be received by the receive logic. The storage controller operates in a single frame mode during the power save mode to process any unsolicited frames. Setting a bit in a configuration register for a processor enables the power save mode. The power save mode is enabled after a memory controller is in a self-refresh mode.

A storage controller includes a first memory that stores a plurality of data blocks that include first and second noncontiguous data segments. A queue module stores data lengths and data start addresses of the first and second data segments. A read assembly module communicates with the first memory and the queue module, receives a request to read the first and second data segments from a host, reads the plurality of data blocks from the first memory, extracts the first and second data segments from the read plurality of data blocks based on the data lengths and data start addresses after the plurality of data blocks is read from the first memory, and transfers the first and second data segments contiguously to the host.

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Mission Viejo, CA, United States of America

Angel G Perozo