Advanced Micro Devices Corporation

Apple Inc.

Ati Technologies Ulc

Advanced Micro Devices (shanghai) Co., Ltd.

Intel Corporation

Ncr Corporation

Angel E Socarras

Michael Mantor

Jeffrey T Brady

Alexander Fuad Ashkar

Rex Eldon McCrary

Bin He

Jiasheng Chen

YunXiao Zou

Wei Yuan

Qingcheng Wang

Thomas A Piazza

Randy Wayne Ramsey

Ralph Clayton Taylor

Kostantinos Danny Christidis

Fei Guo

Harry J Wise

Rashad Oreifej

Gus P Ikonomopoulos

John A Carey

Vivek Oppula

Laurent F Chaouat

Jeffrey D Potter

Mark Russell Anderson

Rohit Gangrade

Safwat Mostafa Noor

Harsh Chakhaiyar

Benoit M Jubelin

Curtis Alan Gilgan

Michael J Mantor

Techniques are disclosed relating to power control and voltage margining. In some embodiments, first and second component circuits operate based on a supply voltage generated by a power supply. Voltage sensor circuitry may generate voltage measurements. Voltage margin control circuitry may determine a voltage ceiling based on a current operating state of the first component circuit and a current operating state of the second component circuit. The control circuitry may transmit control signals to the power supply to incrementally reduce the supply voltage until detecting a low-supply-voltage condition based on a voltage measurement generated by the voltage sensor circuitry. Disclosed techniques may advantageously provide voltage margin while reducing overall power consumption.

Adaptive voltage margin techniques

Techniques are disclosed relating to performing a corrective action in response to certain detected conditions. In disclosed embodiments, clock circuitry is configured to provide a clock signal to processor circuitry. In some embodiments, power monitor circuitry is configured to generate activity information based on activity of different portions of the processor circuitry during operation of the processor circuitry. In some embodiments, machine learning circuitry is configured to predict a future power state of the processor circuitry based on inputs that include the activity information. In some embodiments, control circuitry is configured to, in response to the machine learning circuitry predicting a power state of the processor that falls within a set of one or more target predicted power states, control the clock circuitry to reduce the frequency of the clock signal provided to the processor circuitry.

Power state prediction using machine learning circuitry

Methods and systems are described. A system includes a redundant shader pipe array that performs rendering calculations on data provided thereto and a shader pipe array that includes a plurality of shader pipes, each of which performs rendering calculations on data provided thereto. The system also includes a circuit that identifies a defective shader pipe of the plurality of shader pipes in the shader pipe array. In response to identifying the defective shader pipe, the circuit generates a signal. The system also includes a redundant shader switch. The redundant shader switch receives the generated signal, and, in response to receiving the generated signal, transfers the data for the defective shader pipe to the redundant shader pipe array.

Redundancy method and apparatus for shader column repair

A processing element is implemented in a stage of a pipeline and configured to execute an instruction. A first array of multiplexers is to provide information associated with the instruction to the processing element in response to the instruction being in a first set of instructions. A second array of multiplexers is to provide information associated with the instruction to the first processing element in response to the instruction being in a second set of instructions. A control unit is to gate at least one of power or a clock signal provided to the first array of multiplexers in response to the instruction being in the second set.

Pipeline including separate hardware data paths for different instruction types

Systems, apparatuses, and methods for dynamically adjusting the power consumption of prefetch engines are disclosed. In one embodiment, a processor includes one or more prefetch engines, a draw completion engine, and a queue in between the one or more prefetch engines and the draw completion engine. If the number of packets stored in the queue is greater than a high watermark, then the processor reduces the power state of the prefetch engine(s). By decreasing the power state of the prefetch engine(s), power consumption is reduced. Additionally, this power consumption reduction is achieved without affecting performance, since the queue has a high occupancy and the draw completion engine can continue to read packets out of the queue. If the number of packets stored in the queue is less than a low watermark, then the processor increases the power state of the prefetch engine(s).

Saving power in the command processor using queue based watermarks

Methods, systems and non-transitory computer readable media are described. A system includes a shader pipe array, a redundant shader pipe array, a sequencer and a redundant shader switch. The shader pipe array includes multiple shader pipes, each of which perform rendering calculations on data provided thereto. The redundant shader pipe array also performs rendering calculations on data provided thereto. The sequencer identifies at least one defective shader pipe in the shader pipe array, and, in response, generates a signal. The redundant shader switch receives the generated signal, and, in response, transfers the data destined for each shader pipe identified as being defective independently to the redundant shader pipe array.

A GPU filters graphics workloads to identify candidates for profiling. In response to receiving a graphics workload for the first time, the GPU determines if the graphics workload would require the GPU shaders to use fewer resources than would be spent profiling and determining a resource allocation for subsequent receipts of the same or a similar graphics workload. The GPU can further determine if the shaders are processing more than one graphics workload at the same time, such that the performance characteristics of each individual graphics workload cannot be effectively isolated. The GPU then profiles and stores resource allocations for a plurality of shaders for processing the filtered graphics workloads, and applies those stored resource allocations when the same or a similar graphics workload is received subsequently by the GPU.

System and method for identifying graphics workloads for dynamic allocation of resources among GPU shaders

Apparatuses, computer readable mediums, and methods of processor unit testing using cache resident testing are disclosed. The method may include loading a test program in a cache on a chip comprising one or more processor units. The method may include the one or more processor units executing the test program to generate one or more results. The method may include redirecting a first memory reference to the cache, wherein the first memory reference is generated during the execution of the test program. The method may include determining whether the one or more generated results match one or more test results. The method may include redirecting a memory request to a memory location resident in the cache if the memory request includes a memory location not resident in the cache. The method may include redirecting a memory request to the cache if the memory request is not directed to the cache.

System and method of testing processor units using cache resident testing

An adaptive list stores previously received hardware state information that has been used to configure a graphics processing core. One or more filters are configured to filter packets from a packet stream directed to the graphics processing core. The packets are filtered based on a comparison of hardware state information included in the packet and hardware state information stored in the adaptive list. The adaptive list is modified in response to filtering the first packet. The filters can include a hardware filter and a software filter that selectively filters the packets based on whether the graphics processing core is limiting throughput. The adaptive list can be implemented as content-addressable memory (CAM), a cache, or a linked list.

Adaptive filtering of packets in a graphics processing system

A device and method of operating a synchronous frequency processing environment served by a common power source and common clock source. The method includes operating the processing environment to have a first power consumption. The method further includes determining a first synchronous frequency processing domain within the processing environment where it is desired to implement a first clock frequency alteration in a clock signal for the first synchronous frequency processing domain. The first clock frequency alteration generates an associated first alteration in a power consumption from the first synchronous frequency processing domain. The method further includes determining a second clock frequency alteration to a clock signal for a second synchronous frequency processing domain of the processing environment. The second clock frequency alteration is determined so as to reduce a change in the first power consumption caused by the first alteration in power consumption.

Method and device for noise reduction in multi-frequency clocking environment

A method and apparatus for shader data repair utilizing a Redundant Shader Switch (RSS). The RSS consists of an input and output section whereby when a defective shader pipe is detected, the RSS multiplexes shader pipe data destined to the defective shader pipe to a redundant shader pipe array for processing. Once processed, the shader pipe data is multiplexed back to the RSS where the processed shader pipe data is directed to the corresponding output column of the RSS. The RSS contains delay pipes used to re-align and synchronize the repaired shader pipe data with output export data.

Provided is an apparatus including a scheduler and a plurality of logic devices coupled to the scheduler, each including a defect indicator. The scheduler determines whether one or more of the logic devices is defective based upon its respective defect indicator. The scheduler intentionally omits sending workloads to the disabled logic units, and thus enables the device to be functional albeit at a lower performance or in a differently performing product.

Growing community of inventors

Lake Mary, FL, United States of America

Angel E Socarras