Applied Materials, Inc.

Micro Materials Inc.

Angada Bangalore Sachid

El Mehdi Bazizi

Frank Tzen-Wen Guo

Bhuvaneshwari Ayyagari

Bhuvaneshwari Ayyagari-Sangamalli

Blessy Alexander

Sushant Mittal

He Ren

Susmit Singha Roy

Regina Germanie Freed

Ho-yung David Hwang

Uday Mitra

Madhur Sachan

Ashish Pal

Gabriela Alva

A complete, unified material-to-systems simulation, design, and verification method for semiconductor design and manufacturing may include evaluating effects of semiconductor material or process changes on software algorithms. The method may include generating primitive circuit structures using the material or process changes; performing an electrical characterization of the primitive circuit structures; providing an output of the electrical characterization to a script to generate compact models; generating a digital system based on the compact models; and evaluating a performance of a software algorithm on the digital system to determine an effect of the material or process change for the semiconductor manufacturing process.

Unified material-to-systems simulation, design, and verification for semiconductor design and manufacturing

Processing methods may be performed to form an airgap in a semiconductor structure. The methods may include forming a high-k material on a floor of a trench. The trench may be defined on a semiconductor substrate between sidewalls of a first material and a spacer material. The methods may include forming a gate structure on the high-k material. The gate structure may contact the first material along each sidewall of the trench. The methods may also include etching the first material. The etching may form an airgap adjacent the gate structure.

High performance and low power semiconductor device

Apparatuses and methods to provide a fully self-aligned via are described. A first metallization layer comprises a set of first conductive lines extending along a first direction on a first insulating layer on a substrate, the set of first conductive lines recessed below a top portion of the first insulating layer. A capping layer is on the first insulating layer, and a second insulating layer is on the capping layer. A second metallization layer comprises a set of second conductive lines on the second insulating layer and on a third insulating layer above the first metallization layer. The set of second conductive lines extend along a second direction that crosses the first direction at an angle. At least one via is between the first metallization layer and the second metallization layer. The via is self-aligned along the second direction to one of the first conductive lines. The tapering angle of the via opening may be in a range of from about 60&#xb0; to about 120&#xb0;.

Fully self-aligned via

Semiconductor structures may include a substrate. The structures may include a gate structure overlying the substrate and formed in a first direction across the substrate. The structures may include a fin overlying the substrate and formed in a second direction across the substrate. The second direction may be orthogonal to the first direction, and the fin may intersect the gate structure. The structures may include a source/drain material formed about the fin. The structures may include a through-contact material extending vertically above the source/drain material. The structures may include a metal material extending vertically above the through-contact material. An interface between the metal material and the through-contact material may be characterized by a non-planar profile.

Doped through-contact structures

A complete, unified material-to-systems simulation, design, and verification method for semiconductor design and manufacturing may include evaluating effects of semiconductor material or process changes on software algorithms. The method may include translating the material or process change into a database of characteristics; generating primitive circuit structures using the database of characteristics; performing an electrical characterization of the primitive circuit structures; providing an output of the electrical characterization to a script to generate compact models; generating a lite version of standard cells; generating a digital system based on the lite version of the standard cells; and evaluating a performance of a software algorithm on the digital system to determine an effect of the material or process change for the semiconductor manufacturing process.

A memory circuit may include a memory array, and the memory array may include a plurality of data columns. The plurality of data columns may be configured to store data bits and provide data signals when selected by a read operation. The memory array may also include one or more reference columns distributed in the memory array and configured to provide a reference signal. The reference signal may track with process, voltage, and temperature variations that are specific to the memory array, and may be used to remove a common signal component and adjust the signal level to distinguish between logic 0 and logic 1 data signals.

Narrow range sense amplifier with immunity to noise and variation

A memory circuit includes a memory array with one or more reference columns providing a reference signal and a data column providing a data signal when selected by a read operation. The memory circuit also includes a first circuit that removes a common signal component from the reference signal and from the data signal, along with a second circuit that adjusts the reference signal to be between a logic 1 signal level and a logic 0 signal level. The memory circuit also includes a sense amplifier that determines whether the data signal represents a logic 1 or a logic 0 using the reference signal after the common signal component is removed and after being adjusted, along with the data signal after having the common signal component removed.

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San Jose, CA, United States of America

Angada Bangalore Sachid