Intel Corporation

Angad Narang

Niranjan L Cooray

Salvador Palanca

Subramaniam M Maiyuran

Vladimir M Pentkovski

Steve Tsai

Shekoufeh Qawami

Jagannath Keshava

Praveen B Mosur

Hsien-Hsin Lee

Suresh N Kuttuva

Steve Spangler

A computer system is disclosed. The computer system includes a higher level cache, a lower level cache, a decoder to decode instructions, and a circuit coupled to the decoder. In one embodiment, the circuit, in response to a single decoded instruction, retrieves data from external memory and bypasses the lower level cache upon a higher level cache miss. In another embodiment, the circuit, in response to a first decoded instruction, issues a request to retrieve data at an address from external memory to place said data only in the lower level cache, detects a second cacheable decoded instruction to said address, and places said data in the higher level cache.

Method and apparatus for prefetching data into cache

A method and system for providing cache memory management. The system comprises a main memory, a processor coupled to the main memory, and at least one cache memory coupled to the processor for caching of data. The at least one cache memory has at least two cache ways, each comprising a plurality of sets. Each of the plurality of sets has a bit which indicates whether one of the at least two cache ways contains non-temporal data. The processor accesses data from one of the main memory or the at least one cache memory.

Shared cache structure for temporal and non-temporal instructions

The present invention discloses a method and apparatus for implementing a senior load instruction type. An instruction requesting a memory reference is decoded. The decoded instruction is then dispatched to a memory ordering unit. The instruction is retired from a load buffer and is executed after retiring.

Method and apparatus for load buffers

Method and apparatus for senior loads

Shared cache structure for temporal and non-temporal information using indicative bits

An apparatus and method of optimizing write combining operations using write combining buffers. A plurality of control fields are assigned to each of the write combining buffers. Each of the control fields has a value corresponding to one of a plurality of write combining states. A first of the plurality of write combining states transitions to a second of the plurality of write combining states in response to a write combining operation.

Method and system for optimizing write combining performance in a shared

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Rancho Cordova, CA, United States of America

Angad Narang