Intel Corporation

Ang Li

Eng Hun Ooi

Kuan Hua Tan

Kuan Hau Tan

David J Harriman

Anoop Mukker

Wai Ben Lin

Arash Talebi

Systems and devices can include power management circuitry to manage the entry and exit of active state power management (APSM) link states, such as the transition between an active (L0) state and a low power state (e.g., L1). The power management circuitry can cause a downstream component to initiate an ASPM link state change negotiation based on an ASPM link state change condition being met. An ASPM event analysis logic can identify and track events that occur proximate in time to the ASPM link state change and can correlate the occurrences of the event with ASPM link state changes. An ASPM policy tuning logic can use a correlation between the occurrences of the event and ASPM link state changes to adjust or tune the ASPM link state change condition.

Adaptive lower power state entry and exit

An interface of a device is used to couple to another device and includes a set of data pins to support high speed data communication on an interconnect link between the devices based on an interconnect protocol. The interface further includes at least one auxiliary pin to support a particular signal defined by the interconnect protocol. The device is further configurated to generate hint data for use by the other device and send the hint data as a sideband signal to the other device over the auxiliary pin, where the sideband signal is distinct from signals defined for the auxiliary pin by the interconnect protocol.

Sideband signaling over existing auxiliary pins of an interface

A device connected by a link to a host system can include a first port to receive a capability configuration message across a link and a message request receiving logic comprising hardware circuitry to identify a capability of the device identified in the capability configuration message, determine that the capability is to be presented or hidden from operation based on a capability hide enable bit in the capability configuration message, and configure a capability linked list to present or hide the capability based on the determination. The device can also include a message response generator logic comprising hardware circuitry to generate a response message indicating that the capability is to be presented or hidden from operation. The device can include a second port to transmit the response message across the link.

Dynamic presentation of interconnect protocol capability structures

Methods and apparatus for optimizing device power and efficiency based on host-controlled hints prior to low-power entry for PCI Express blocks and components. Data structures containing low-power state capability information mapping one or more fine-grained low-power states for each of at least one of an L0s, L1, L1.1, and L1.2 PCIe-defined low-power state are stored on a PCIe device coupled to a Host via a PCIe link. Messages are exchanged over the PCIe link between the Host and PCIe device to configure, using the low-power state capability information, blocks and/or components on the PCIe device to enter a fine-grained low-power state instead of an associated PCIe-defined low-power state mapped to the fine-grained low-power state when the PCIe device detects a power-change event or receives a command to enter the associated PCIe-defined low-power state. Sequences of power-level changes between multiple fine-grained low-power states may also be implemented.

Method of optimizing device power and efficiency based on host-controlled hints prior to low-power entry for blocks and components on a PCI express device

Methods, apparatus, and systems for securely providing multiple wake-up time options for PCI Express (PCIe) devices. Under one approach, Vendor Define Messages (VDMs) are exchanged between a host application layer in a host and a device application layer in a PCIe endpoint device coupled to the host via a PCIe link to effect changes to the L1.2 Substate exit time of a PCIe device. Under another approach, Vendor-Specific Extended Capability (VSEC) structures are exchanged between a host application layer and a device application layer to effect the changes. The VDMs and VSEC structures may also be used to enable a host to read Tpower_on capability information defining power modes supported by a PCIe device. Additionally, VSEC implementations are provided that implement VSEC components in the PCIe device transaction layer or the PCIe device application layer.

Securely providing multiple wake-up time options for PCI Express

A handshake communication mechanism between a host and an end-point device permits multiple Base Address Registers (BAR registers) to be configured to size or resize the mapped address spaces associated with each BAR register. In one embodiment, the handshake communication mechanism includes a single address space reconfiguration request which may be transmitted in a single transaction layer packet, to request the configuration of multiple BAR registers of an end-point device. Other features and advantages may be realized, depending upon the particular application.

Memory resource allocation in an end-point device

Systems and devices can include a power management controller to determine a low power mode exit timing from a plurality of low power mode exit timing options, and cause the setting of a low power mode control register based on the determined low power mode exit timing. A message generator can generate a power mode request message. The power mode request message indicating the determined low power mode exiting timing. The power mode request message can be transmitted to a host across a multilane link.

Providing multiple low power link state wake-up options

Devices, systems, and methods for transferring data between the memory domain and the storage domain are described. Transferring data between domains can comprise changing the validity of the block address of the data from one domain to the other, and updating a memory domain map and a storage domain map to reflect the transfer.

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Coquitlam, Canada

Ang Li