Infinite Memory Ltd.

Infinite Memories Ltd.

Aner Arussi

Eli Lusky

Amir Gabai

Disclosed is a method, circuit and system for determining a Lowest Operative Threshold Voltage Level for one or more cell segments/blocks/sets of a NVM array and a corresponding device, adapted to compare substantially native state NVM cells in a block of cells against one or more reference cells/structures or offset values, and to maintain a read error count.

Method circuit and system for operating an array of non-volatile memory ('NVM') cells and a corresponding NVM device

A memory chip includes memory cells storing data to be read, at least one reference cell having a reference cell current level, at least one reference gate voltage memory cell storing a reference gate voltage value and a read circuit to read the memory cells with a fixed gate voltage with respect to at least one reference cell activated at a voltage having its associated stored reference gate voltage value.

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Alfei-Menashe, Israel

Aner Arussi