Applied Materials, Inc.

Leland Stanford Junior University

Aneesh Nainani

Mathew Abraham

Er-Xuan Ping

Krishna Chandra Saraswat

Joseph Michael Ranish

Aaron Muir Hunter

Shahid Rauf

Leonid Dorf

Joseph R Johnson

Adam Brand

John Gerling

Subhash Deshmukh

Bhushan N Zope

Ashish Pal

Provided are methods of doping substrates and making doped semiconductor features. An exemplary method includes providing a substrate having at least one feature having an aspect ratio; depositing a layer of dopants onto the substrate, the layer of dopants having a shape conforming to the at least one feature. A dielectric layer is deposited onto the layer of dopants, the dielectric layer having a shape conforming to the layer of dopants. The dielectric layer is annealed to diffuse the dopants into the substrate.

Methods of doping substrates with ALD

Apparatus for providing heat energy to a process chamber are provided herein. The apparatus may include a process chamber body of the process chamber, a solid state source array having a plurality of solid state sources, disposed on a first substrate, to provide heat energy to the process chamber to heat a target component disposed in the process chamber body, and at least one reflector disposed on the first substrate proximate to one or more of the plurality of solid state sources to direct heat energy provided by the one or more of the plurality of solid state sources towards the target component.

Apparatus for providing and directing heat energy in a process chamber

An electron beam plasma source is used in a soft plasma surface treatment of semiconductor surfaces containing Ge or group III-V compound semiconductor materials.

Interface treatment of semiconductor surfaces with high density low energy plasma

Various aspects of the invention are directed to memory circuits and their implementation. According to an example embodiment, an apparatus includes a channel region between raised source and drain regions which are configured and arranged with respective bandgap offsets relative to the channel region to confine carriers in the channel region. The apparatus also includes front and back gates respectively separated from the channel region by gate dielectrics. The raised source and drain regions have respective portions laterally adjacent the front gate and adjacent the channel region. Carriers are stored in the channel region via application of voltage(s) to the front and back gates, and relative to bias(es) at the source and drain regions.

Transistor-based apparatuses, systems and methods

In accordance with one or more embodiments, an apparatus and method involves a channel region, barrier layers separated by the channel region and a dielectric on one of the barrier layers. The barrier layers have band gaps that are different than a band gap of the channel region, and confine both electrons and holes in the channel region. A gate electrode applies electric field to the channel region via the dielectric. In various contexts, the apparatus and method are amenable to implementation for both electron-based and hole-based implementations, such as for nmos, pmos, and cmos applications.

Heterostructure field effect transistor with same channel and barrier configuration for PMOS and NMOS

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Palo Alto, CA, United States of America

Aneesh Nainani