Alcatel Lucent

Alcatel Internetworking, Inc.

Xylan Corporation

Anees Narsinh

John W Bailey

Drew Bertagna

Marc-Alain Santerre

Robert Dexter

Jean-Francois Cartier

Paul Chi

James A Hitzelberger

Levillain Philippe

The present invention features a data link layer processor for performing VLAN tagging operations, policing, shaping, and statistics acquisition integrally with one or more media access controllers (MACs). When a plurality of data link layer processors are operated in parallel in a switching device, the computational burden carried by the route engine is significantly reduced. Moreover, the data link layer processor in its several embodiments may be used to introduce various forms of pre-processing and post-processing into network switching systems that employ route engines that do not posses such functionality.

Parallel data link layer controllers in a network switching device

A switch in a data communications network for performing traffic generation in addition to standard switching and routing operations is disclosed. The switch uses a fixed number of test packets retained in a conventional switch buffer to produce one or more infinite packet streams transmitted to a router under test (RUT). The switching device enqueues packets in the priority queues, dequeues the packets from the priority queues, transmits the dequeued packets to the RUT, and re-enqueues a copy of the dequeued packets into the priority queues from which they were dequeued. The enqueued packets and associated pointers to packets are organized into linked lists. By re-writing a copy of each dequeued packet to the tail of a linked list and updating the pointers, the switch produces repeatable streams of test packets. The priority buffers, without the re-write operation, may also be used for conventional egress traffic.

Traffic generator and monitor

The present invention features a data link layer processor for performing VLAN tagging operations, policing, shaping, and statistics acquisition integrally with one or more media access controllers (MACs). When a plurality of data link layer processors are operated in parallel in a switching device, the computational burden carried by the route engine is significantly reduced. Moreover, the data link layer processor in its several embodiments may be used to introduce various forms of pre-processing and post-processing into network switching systems that employ route engines that do not possess such functionality.

A protocol translation hardware assist for resolving protocol incompatibilities in a multi-protocol switching environment. Discrete information units are transferred seamlessly from inputs to disparate protocol outputs by writing inbound discrete information units into selected address spaces in allocated buffers in a transfer queue in a manner which accounts for protocol format differences while allowing for straightforward dequeueing. The hardware assist fragments inbound discrete information units into multiple outbound units and creates offsets indicated by destination protocol requirements. A bypass check may be implemented to avoid subjecting to the fragmentation inquiry discrete information units for which it can be inferred a priori that fragmentation is not required.

Translation hardware assist for data communication switch

A data transfer system efficiently allocates contiguous address spaces in a destination storage area to packets by maintaining a plurality of lists from which different amounts of contiguous address spaces are allocated. List selection is made based on known or presumed packet characteristics. By arranging different lists to supply contiguous address spaces in different amounts based on packet-specific characteristics, over-allocation of address space may be reduced considerably while contiguous address space is guaranteed on a continuous basis.

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Pacific Palisades, CA, United States of America

Anees Narsinh