Arm Limited

Andy Wangkun Chen

Yew Keong Chong

Sriram Thyagarajan

Ayush Kulshrestha

Sony

Gus Wai-Yan Yeung

Mudit Bhargava

Rahul Mathur

Rajiv Kumar Sisodia

Munish Kumar

Ettore Amirante

Marlin Wayne Frederick, Jr

Hsin-Yu Chen

Bo Zheng

Vivek Asthana

Frank David Frederick

Brian Tracy Cline

Lalit Gupta

Akshay Kumar

Bikas Maiti

Cyrille Nicolas Dray

Vivek Nautiyal

Jitendra Dasani

Xiaoqing Xu

Teresa Louise McLaurin

Richard Slobodnik

Vianney Antoine Choserot

Yannis Jallamion-Grive

Shardendu Shekhar

Khushal Gelda

Akash Bangalore Srinivasa

Penaka Phani Goberu

Tom Shore

Yicong Li

George McNeil Lattimore

Fakhruddin Ali Bohra

Vikash

James Dennis Dodrill

Sanjay Mangal

Paul Christopher De Dood

Kumaraswamy Ramanathan

Daniel J Albers

Pratik Ghanshambhai Satasia

Ronald Paxton Preston

David William Granda

Jerry Chaoyuan Wang

Peixuan Tan

James Edward Myers

Vikas Chandra

Michael Filippo

Paul Gilbert Meyer

Edward Martin McCombs, Jr

Alex James Waugh

Saurabh Pijuskumar Sinha

Shri Sagar Dwivedi

Nicolaas Klarinus Johannes Van Winkelhoff

Pranay Prabhat

Supreet Jeloka

Joel Thornton Irby

Andrew John Turner

Jungtae Kwon

Martin Jay Kinkade

Anil Kumar Baratam

Amandeep Kaur

Arjun Singh

Mouli Rajaram Chollangi

Jonas Švedas

Mohit Chanana

Shruti Aggarwal

Thanusree Achuthan

Kyung Woo Kim

Ramesh Manohar

Graham Peter Knight

Gaurang Prabhakar Narvekar

Yanbin Jiang

Indranil Basu

Prashant Mohan Kulkarni

Sharryl Renee Dettmer

Sreebin Sreedhar

Vibin Vincent

Balaji Ravikumar

Sai Sriharsha Manapragada

Mohammed Saif Kunjatur Sheikh

Sabarish Ittamveetil

Yann Sarrazin

Julien Vincent Poitrat

Sylvia Xiuhui Li

Matthieu Domonique Henri Pauly

Emmanuel Jean Marie Olivier Pacaud

Brian Douglas Ngai Lee

Abhishek Baradia

Cagla Cakir

Yeon Jun Park

Inrush current in a memory such as SRAM cache may be managed by using one or more integrated delay elements such as inverters, RC delay lines, and the like to significantly slow down power down signal propagation between memory instances in a memory array. The delay in some examples may be between memory instances, while in other examples the delay is also introduced between bitcell arrays within a memory instance. By staggering the power up times of interconnected or chained memory instances, inrush current when powering the memory instances on or resuming from an inactive state may be reduced.

Inrush current management in a memory array

Various implementations described herein are directed to a device having a bank of bitcells split into a plurality of portions including a first row slice of the bitcells and a second row slice of the bitcells. Also, the device may have control circuitry configured to access and repair a first bitcell in the first row slice with a first row address and a second bitcell in the second row slice with a second row address that is different than the first row address.

Row repair circuitry

A memory instance comprises a plurality of banks of storage cells to store data values, and input/output circuitry shared between the plurality of banks for receiving write data or outputting read data. Each bank of storage cells supports a power saving mode and an operational mode. A control interface receives power control signals for controlling use of the power saving mode. Bank power control circuitry individually controls, for each of a plurality of subsets of banks of storage cells within the same memory instance, whether that subset of banks is in the power saving mode based on the power control signals. For at least one setting for the power control signals, one subset of banks is in the power saving mode while another subset of banks in the same memory instance is in the operational mode. Also disclosed is power control circuitry which selects the power mode to use for each subset of banks and generates the power control signals.

Power saving mode control for a memory instance

Various implementations described herein are related to a device having first datapath circuitry with input devices that receive data from a number of write ports and provide first data. The device may have second datapath circuitry with logic gates that receive the first data from the input devices and provide the first data based on a read bitline signal. The device may have third datapath circuitry with output devices that receive the first data from the logic gates and provide second data to a number of read ports. Also, the number of read ports is greater than the number of write ports.

Configurable scan chain architecture for multi-port memory

Various implementations described herein are related to a device having a storage node with a bitcell. The device may have a first stage that performs a first write based on an internal bitline signal, a first write wordline signal and a second write wordline signal. The first stage outputs the internal bitline signal. The device may have a second stage that receives the internal bitline signal and performs a second write of the internal bitline signal to the bitcell. The device may have a third stage with write wordline ports and write bitline ports. The third stage provides the internal bitline signal based on a selected write wordline signal from a write wordline port of the write wordline ports and based on a selected bitline signal based on a write bitline port of the write bitline ports.

Multi-port bitcell architecture

Various implementations described herein are related to a device having logic that operates in multiple voltage domains. The device may include a backside power network with rows of segmented supply rails coupled to the logic. The rows of segmented supply rails may include alternating rail breaks that define an interchanging directional supply of power to the logic in the multiple voltage domains.

Backside power supply techniques

Various implementations described herein are directed to a method for identifying pre-routed metal lines in a higher layer of a multi-layered structure. The method may recognize gaps in the pre-routed metal lines of the higher layer, and also, the method may automatically fill the gaps with conductive stubs to modify the pre-routed metal lines in the higher layer as a continuous metal line with an extended length.

Metal routing techniques

Various implementations described herein are directed to a device having memory circuitry having multi-port bitcells, wherein each bitcell of the multi-port bitcells has a read-write port and a read port. The device may have read-write circuitry coupled to the read-write port, wherein the read-write circuitry has write-drive logic and read-sense logic that provide for at least one write and at least one read in a single clock cycle.

Multi-port memory architecture

According to one implementation of the present disclosure, an integrated circuit includes comparator circuitry coupled to peripheral circuitry of a multiport memory and configured to transmit one or more data input signals or one or more write enable signals to respective memory outputs when a memory address collision is detected for one or more respective bitcells of the multi-port memory. In another implementation, a method comprises: detecting a read operation and a write operation to a same memory bitcell of a multiport memory in one clock cycle and in response to the detection, performing the read operation of a data input signal or a write enable signal of the multiport memory.

Circuitry for memory address collision prevention

Various implementations described herein are related to a device having multi-port circuit architecture with multiple ports. The multi-port circuit architecture may expand a primary clock into multiple dummy clocks so as to separately track, simulate and report clock power consumption for each port of the multiple ports to a central processing unit.

Multi-port circuit architecture

Various implementations described herein are related to a device having multiple transistors that are arranged as a bitcell. The device may include multiple wordlines that are coupled to the multiple transistors. Also, one or more wordlines may be formed with frontside metal, and one or more other wordlines may be formed with buried metal.

Bitcell architecture using buried metal

Various implementations described herein are related to a method for accessing a bitcell in an array of bitcells with a wordline and a bitline. The method may perform a precharge operation on the bitline that precharges the bitline after a read cycle and before a write cycle. Also, the method may extend precharge time of the precharge operation between the read cycle and the write cycle, e.g., by modulating a wordline signal on the wordline with early cut-off of the wordline signal on the wordline during the read cycle.

Wordline modulation techniques

Various implementations described herein refer to a device having an encoder coupled to memory. The ECC encoder receives input data from memory built-in self-test circuitry, generates encoded data by encoding the input data and by adding check bits to the input data, and writes the encoded data to memory. The device may have an ECC decoder coupled to memory. The ECC decoder reads the encoded data from memory, generates corrected data by decoding the encoded data and by extracting the check bits from the encoded data, and provides the corrected data and double-bit error flag as output. The ECC decoder has error correction logic that performs error correction on the decoded data based on the check bits, wherein if the error correction logic detects a multi-bit error in the decoded data, the error correction logic corrects the multi-bit error in the decoded data to provide the corrected data.

Memory testing techniques

Various implementations described herein are related to various devices having a frontside power network with frontside supply rails and a backside power network with backside supply rails. The device may include intermixing architecture with transition vias that couple the frontside power network to the backside power network. The intermixing architecture may transition the frontside supply rails of the frontside power network to the backside supply rails of the backside power network.

Frontside-to-backside intermixing architecture for coupling a frontside network to a backside network

A compressor includes a logic circuit having transistors of a first channel type to receive a plurality of bit signals, and transistors of a second channel type, different from the first channel type, to receive the plurality of bit signals. The transistors of the first channel type are configured to generate an XOR logic output based on the plurality of bit signals, and the transistors of the second channel type are configured to generate, substantially simultaneous with the generation of the XOR logic output, an XNOR logic output based on the plurality of bit signals. The compressor includes NAND gates to receive multiplicand and multiplier bit signals.

Data compressor logic circuit

Growing community of inventors

Austin, TX, United States of America

Andy Wangkun Chen