Triquint Semiconductor Corporation

Other

Altera Corporation

Rancho Del I.p.

Andy Turudic

William H Davenport

Sergey Yuryevich Shumarayev

Bruce B Pedersen

David Wolk Mendel

Tim Tri Hoang

Gary Alan Evans

Edward A Beam, Iii

Kumara Tharmalingam

Paul Saunier

Michael Menghui Zheng

Allan Thomas Davidson

Neville Carvalho

Ming-Yih Kao

David Michael Fanning

Walter Anthony Wohlmuth

Kalyan Kankipati

Seungmyon Park

David E McNeill

An ultra low cost electric vehicle heating apparatus, components thereof, and related method are herein described. A driver circuit operates a switching device at an intermediate state between fully-turned-off and fully-turned-on, in a high power dissipation heating mode, to efficiently produce heat energy for heating a passenger compartment, or energy storage system, of an electric vehicle. The driver circuit operates the switching device to have a fully-turned-off state and a fully-turned-on state in a main function mode for a traction inverter or an energy storage system charger of the electric vehicle. The driver circuit is operable to cycle the heating mode and the main function mode for combining such heating and such main function operation of the traction inverter, or the charger, without compromising the operation of the traction motor, or charger, while simultaneously eliminating many of the expensive resistive heating components in use by practitioners of the art.

Electric vehicle thermal management and safety apparatus

Selective efficiency multi-phase traction inverters and chargers as heat sources for thermal conditioning of electric vehicles is provided. The traction inverter comprises a plurality of phases, each of the plurality of phases having at least one semiconductor switching device, the at least one semiconductor switching device configured to switch between at least three differing states, for thermal management of the electric vehicle components and compartments. The traction inverter includes a controller coupled to the plurality of phases, to operate the plurality of phases in a first mode of the traction inverter to drive the electric motor as a traction motor. The controller operates the plurality of phases in a second mode of the traction inverter as a first type of converter. The controller to operate the plurality of phases in a third mode of the traction inverter as a second type of converter.

Selective efficiency traction inverters and chargers as heat sources for thermal conditioning of electric vehicles

Ultra-low-cost coolant heating apparatus for electric vehicle applications

A lamp is provided. The lamp includes at least one light emitting diode (LED) and an electronic circuit configured to provide power to the at least one LED. The lamp includes at least one flat circuit board having mounted thereto the at least one LED and the electronic circuit. The at least one flat circuit board acts as a heatsink to dissipate heat from the at least one LED and acts as a plurality of circuit paths for the electronic circuit and the at least one LED.

2-D lamp with integrated thermal management and near-ideal light pattern

A transceiver system with reduced latency uncertainty is described. In one implementation, the transceiver system has a word aligner latency uncertainty of zero. In another implementation, the transceiver system has a receiver-to-transmitter transfer latency uncertainty of zero. In yet another implementation, the transceiver system has a word aligner latency uncertainty of zero and a receiver-to-transmitter transfer latency uncertainty of zero. In one specific implementation, the receiver-to-transmitter transfer latency uncertainty is eliminated by using the transmitter parallel clock as a feedback signal in the transmitter phase locked loop (PLL). In one implementation, this is achieved by optionally making the transmitter divider, which generates the transmitter parallel clock, part of the feedback path of the transmitter PLL. In one implementation, the word aligner latency uncertainty is eliminated by using a bit slipper to slip bits in such a way so that the total delay due to the word alignment and bit slipping is constant for all phases of the recovered clock. This allows for having a fixed and known latency between the receipt and transmission of bits for all phases of parallelization by the deserializer. In one specific implementation, the total delay due to the bit shifting by the word aligner and the bit slipping by the bit slipper is zero since the bit slipper slips bits so as to compensate for the bit shifting that was performed by the word aligner.

Transceiver system with reduced latency uncertainty

One or two Serializer/Deserializer (SerDes) modules are used to measure the time between two pulses with high resolution. A PLL inside a SerDes block is locked to a reference clock and an input signal is passed through a storage element to create a serial data stream that is converted into a parallel data stream by a demultiplexer inside the SerDes. The parallel data is stored in a bit logic unit that compares the parallel data to a second parallel data obtained in similar fashion in another SerDes from a second input signal. The time between the two pulses is then calculated as the number of cycles in the serial data stream that corresponds to the number of bits between the positions of the two events.

Method and apparatus for precision quantization of temporal spacing between two events

A method for aligning output from a first transmit source and a second transmit source is provided. The method includes combining complementary portions of differential signals generated from respective transmit sources to generate an output bit sequence and comparing the output bit sequence with an input bit sequence used to generate the differential signals. The method further includes adjusting one of the first or the second transmit source based on the comparison to align the output from the first and the second transmit sources. A PLD having the capability to align channels of different octets is also provided.

Phase-detector-less method and apparatus for minimizing skew between bonded channel groups

A light-emitting device includes a GaAs substrate, a light-emitting structure disposed above the substrate and capable of emitting light having a wavelength of about 1.3 microns to about 1.55 microns, and a buffer layer disposed between the substrate and the light-emitting structure. The composition of the buffer layer varies through the buffer layer such that a lattice constant of the buffer layer grades from a lattice constant approximately equal to a lattice constant of the substrate to a lattice constant approximately equal to a lattice constant of the light-emitting structure. The light-emitting device exhibits improved mechanical, electrical, thermal, and optical properties compared to similar light-emitting devices grown on InP substrates.

Long wavelength laser diodes on metamorphic buffer modified gallium arsenide wafers

An improved phase-locked loop circuit includes a variable-frequency oscillator that generates a first oscillator signal, a reference signal source that generates a second oscillator signal, a control block that generates a select signal, and a frequency divider that receives as an input signal one of the first and second oscillator signals. The frequency divider also receives the select signal from the control block. The frequency divider generates a plurality of frequency-divided signals in response to the input signal, and passes through a selected one of the plurality of frequency-divided signals as an output signal in response to the select signal. The frequency divider also synchronizes its output signal to its input signal. The phase-locked loop also includes a frequency comparator that receives the output signal of the frequency divider and a signal derived from one of the first and second oscillator signals. The frequency comparator compares the output signal of the frequency divider to the signal derived from one of the first and second oscillator signals, and provides a feedback signal to the variable-frequency oscillator reflecting this comparison. In this phase-locked loop circuit, the number of signal regenerators introduced by the programmable frequency divider is effectively limited to one, thereby reducing the jitter introduced by the frequency divider.

Phase-locked loop circuit with reduced jitter

A multiplexer includes a first input device that receives a first input signal and a first select signal. When the first select signal has a first state, the first input device generates a first voltage at a first node in response to the first input signal. When the first select signal has a second state, the first input device generates a first reference voltage at the first node. A second input device receives a second input signal and a second select signal related to the first select signal. When the second select signal has a first state, the second input device generates a second voltage at a second node in response to the second input signal. When the second select signal has a second state, the second input device generates a second reference voltage at the second node. A first output buffer has an input terminal coupled to the first node and an output terminal coupled to an output node. The first output buffer tracks the first voltage at the output terminal, and presents a high impedance at the output terminal when the first reference voltage is present at the first node. A second output buffer has an input terminal coupled to the second node and an output terminal coupled to the output node. The second output buffer tracks the second voltage at the output terminal, and presents a high impedance at the output terminal when the second reference voltage is present at the second node.

Differential multiplexer with high bandwidth and reduced crosstalk

A method is disclosed for attaching a device package to a circuit board with a chip mount area that has a set of elongated pads located near the perimeter of a chip mount area. In accordance with this method, a mask is formed on the circuit board. A plurality of openings are formed in the mask, including a plurality of openings over at least one of the pads. A plurality of adhesive masses area attached to a surface of the device package, each adhesive mass being aligned with an electrical contact area on the surface of the device package. The device package is positioned over the circuit board to align the adhesive masses with the openings in the mask, and the device package is attached to the circuit board. In one embodiment, the mask openings are formed in a staggered formation. An advantage of this method is that a less expensive chip of the ball grid array type may be used on a circuit board design for gull-wing-leaded chip packages without a substantial redesign of the circuit board. The invention also allows ball grid array-type packages and gull-wing leaded chip packages to be used interchangeably for the same circuit board design with only a modification of the mask used in the circuit board fabrication process.

Growing community of inventors

Hillsboro, OR, United States of America

Andy Turudic