Advanced Micro Devices Corporation

Andy Steinbach

Michael T Wisor

Scott E Swanstrom

A computing system and bus bridge in which the bus bridge includes a buffer pool wherein the storage buffers contained in the buffer pool may be allocated as post buffers or fetch buffers in response to appropriate requests from the bus bridge. In the preferred embodiment, the bus bridge includes a buffer pool control unit adapted to temporarily allocate any of the plurality of storage buffers as either a post buffer or a fetch buffer depending upon the system requirements. Broadly speaking, the present invention contemplates a computing system including a first component connected to a first bus, a second component connected to a second bus, and a bus bridge connected to a first and second busses. The bus bridge includes a buffer pool comprised of a plurality of storage buffers and a buffer pool control unit that is capable of temporarily allocating at least one of the storage buffers as either a post buffer or a fetch buffer in response to system requirement. Preferably, each storage buffer includes corresponding tag information for identifying an origin or destination location within a main memory of the data associated with the storage buffer. In one embodiment, each of the plurality of storage buffers includes corresponding allocation information used by the buffer pool control unit for the temporary allocation of the storage buffers. In a presently preferred embodiment, the allocation information includes an available bit indicative of whether the storage buffers available for allocation and a post/fetch bit indicative of whether an unavailable storage buffer is currently allocated as a post buffer or as a fetch buffer. The allocation information is accessible by the buffer pool control unit and is used by the buffer pool control unit for temporarily allocating the storage buffers.

Allocatable post and prefetch buffers for bus bridges

A cache memory system comprising a first bus for connecting to a bus master and a second bus for connecting to a system memory. The system memory comprises a plurality of cacheable memory locations. A bus bridge provides an interface between the first bus and the second bus. A cache memory controller for caching data stored in the cacheable memory locations is connected to the system memory. The cache memory controller includes a snoop control circuit directly coupled to the first bus for snooping bus transactions upon the first bus and further coupled to the second bus for snooping bus transactions on said second bus.

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Austin, TX, United States of America

Andy Steinbach