Intel Corporation

Andy M Rudoff

Rajesh M Sankaran

Wei P Chen

Murugasamy K Nachimuthu

Rajat Agarwal

Mahesh S Natu

Tiffany J Kasanicky

Scott W Kirvan

Mark A Schmisseur

Sreenivas Subramoney

Ishwar Agarwal

Richard Paul Mangold

Alaa R Alameldeen

Gideon Gerzon

Chet R Douglas

Lidia Warnes

Zhe Wang

Muthukumar Swaminathan

Woojong Han

Vivekananthan Sanjeepan

Aravinda Prasad

Douglas E Stewart

Sandeep Kumar

Wei Chen

Disclosed Methods, Apparatus, and articles of manufacture to profile page tables for memory management are disclosed. An example apparatus includes a processor to execute computer readable instructions to: profile a first page at a first level of a page table as not part of a target group; and in response to profiling the first page as not part of the target group, label a data page at a second level that corresponds to the first page as not part of the target group, the second level being lower than the first level.

Methods and apparatus to profile page tables for memory management

A memory management system includes a cache invalidation logic configured to invalidate, based a cache invalidation event, cache entries within a cache memory by having each cache entry, of the cache entries within the cache memory, reference a respective dummy address from among dummy addresses within a dummy address space, wherein the cache memory is assigned to a memory, the memory has a memory address space associated therewith to provide access the memory, and each dummy address of the dummy addresses within the dummy address space is distinct from any address of the memory address space.

Memory system, computing system, and methods thereof for cache invalidation with dummy address space

A two-level main memory that includes a persistent memory and a cache is provided. Locations of dirty cache lines in the cache are tracked through the use a dirty cache line tracker. The dirty cache line tracker is stored in the cache and can be cached in a memory controller for the persistent memory. The dirty cache line tracker can be used to bypass cache lookup, perform efficient dirty cache line scrubbing and to decouple battery power and capacity of the cache in the two-level main memory.

Method and apparatus to efficiently track locations of dirty cache lines in a cache in a two-level main memory

According to various aspects, a memory system may include: a memory having a memory address space associated therewith to access the memory; a cache memory assigned to the memory; one or more processors configured to generate a dummy address space in addition to the memory address space, each address of the dummy address space being distinct from any address of the memory address space, and generate one or more invalid cache entries in the cache memory, the one or more invalid cache entries referencing one or more dummy addresses of the dummy address space.

Methods and apparatus to allocating and/or configuring persistent memory are described. In an embodiment, memory controller logic configures non-volatile memory into a plurality of partitions at least in part based on one or more attributes. One or more volumes (visible to an application or operating system) are formed from one or more of the plurality of partitions. Each of the one or more volumes includes one or more of the plurality of partitions having at least one similar attribute from the one or more attributes. In another embodiment, memory controller logic configures a Non-Volatile Memory (NVM) Dual Inline Memory Module (DIMM) into a persistent region and a volatile region. Other embodiments are also disclosed and claimed.

Allocating and configuring persistent memory

Provided are an apparatus and method for using block windows configured in a memory module to provide block level access to memory chips in the memory module. A plurality of block windows are configured that map to addresses corresponding to the addressable locations in the memory chips. A read/write request is received indicating a requested read or write operation with respect to a target block window comprising one of the block windows. The requested read or write operation is performed with respect to the addresses that map to the target block window.

Apparatus and method to support a storage mode over a cache-line memory interface to a non-volatile memory dual in line memory module

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Boulder, CO, United States of America

Andy M Rudoff