Intel Corporation

Andy Groves

David G Ellis

Gary W Brady

Each data sending high speed circuit generating and sending a stream of data slices and a stream of clock pulses is provided with a sync pulse generation circuit for synchronously generating and sending an accompanying stream of periodic sync pulses. The various streams of data slices, clock pulses, and periodic sync pulses incur varying amount of delays as they travel from the data sending high speed circuits to a data acquisition circuit. The data acquisition high speed circuit is provided with a plurality of circular buffer chains of appropriate length for independently buffering the skewed data slices until all corresponding data slices have been received and buffered, and then concurrently reading the buffered corresponding data slices out of the circular buffer chains. The data acquisition high speed circuit is also provided with a plurality of corresponding independent write address generators and a common read address generator for generating the independent write buffer addressed and the synchronized read buffer addresses using the data clocks and the periodic sync pulses. As a result, the skewed data slices are deskewed or resynchronized as they are read out of the circular buffer chain.

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Hillsboro, OR, United States of America

Andy Groves