Intel Corporation

Andy Glew

Gilbert A Neiger

Richard A Uhlig

Michael A Kozuch

Lawrence O Smith

Clifford D Hall

David I Poisner

David W Grawrock

James A Sutton, Ii

Robert T George

Bradley Gene Burgess

Glenn J Hinton

Andrew V Anderson

Steven M Bennett

Haitham H Akkary

Nitin V Sarangdhar

Erik C Cota-Robles

Dion Rodgers

Sebastian Schoenberg

Stalinselvaraj Jeyasingh

Mandar S Joshi

Alain Kagi

Erich Boleyn

Eric C Cota-Robles

A method and apparatus for sharing translation buffer entries between multiple processing resources is herein described. A sharing field in a translation entry is to represent that the translation entry is to be associated with/shared between a plurality of processing resources, if the translation entry is determined to be the same for the plurality of processing resources. Upon a miss to a translation buffer associated with a first resource, a new translation for the first resource is completed. The new translation is compared to other entries in the translation buffer to determine if any other entries include the same translation for other resources. In response to determining other resources are associated with the same translation, a sharing field in a translation entry is to indicate which resources the entry is to be associated with/shared between.

Means to share translation lookaside buffer (TLB) entries between different contexts

One embodiment of the present invention is a technique to invalidate entries in a translation lookaside buffer (TLB). A TLB in a processor has a plurality of TLB entries. Each TLB entry is associated with a virtual machine extension (VMX) tag word indicating if the associated TLB entry is invalidated according to a processor mode when an invalidation operation is performed. The processor mode is one of execution in a virtual machine (VM) and execution not in a virtual machine. The invalidation operation belongs to a non-empty set of invalidation operations composed of a union of () a possibly empty set of operations that invalidate a variable number of TLB entries, () a possibly empty set of operations that invalidate exactly one TLB entry, () a possibly empty set of operations that invalidate the plurality of TLB entries, () a possibly empty set of operations that enable and disable use of virtual memory, and () a possibly empty set of operations that configure physical address size, page size or other virtual memory system behavior in a manner that changes the manner in which a physical machine interprets the TLB entries.

Invalidating translation lookaside buffer entries in a virtual machine (VM) system

An apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment are described. The method includes disregarding a received load secure region instruction when a currently active load secure region operation is detected. Otherwise, a memory protection element is directed, in response to the received load secure region instruction, to form a secure memory environment. Once directed, unauthorized read/write access to one or more protected memory regions are prohibited. Finally, a cryptographic hash value of the one or more protected memory regions is stored within a digest information repository as a secure software identification value. Once stored, outside agents may request access to a digitally signed software identification value to establish security verification of secure software within the secure memory environment.

Apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment

In one embodiment, a method includes transitioning control to a virtual machine (VM) from a virtual machine monitor (VMM), determining that a VMM timer indicator is set to an enabling value, and identifying a VMM timer value configured by the VMM. The method further includes periodically comparing a current value of a timing source with the VMM timer value, generating an internal event if the current value of the timing source has reached the VMM timer value, and transitioning control to the VMM in response to the internal event without incurring an event handling procedure in any one of the VMM and the VM.

System and method for controlling switching between VMM and VM using enabling value of VMM timer indicator and VMM timer value having a specified time

A method and an apparatus are used to efficiently translate memory addresses. The translation scheme yields a translated address, a memory type for the translated address, and a fault bit for the translation.

Method and apparatus for translating guest physical addresses in a virtual machine environment

An apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment are described. The method includes disregarding a received load secure region instruction when a currently active load secure region operation is detected. Otherwise, a memory protection element is directed, in response to the received load secure region instruction, to form a secure memory environment. Once directed, unauthorized read/write access to one or more protected memory regions are prohibited. Finally, a cryptographic hash value of the one or more protected memory regions is stored within a digest information repository as a secure software identification value. Once stored, outside agents may request access to a digitally signed software identification value in order to establish security verification of secure software within the secure memory environment.

A page table walk is performed in response to a data translation lookaside buffer miss based on a speculative memory instruction. In the event of a data translation lookaside buffer miss, a page miss handler determines whether the memory micro-instruction causing the miss is a speculative or non-speculative micro-instruction. If non-speculative, the page miss handler performs a non-speculative page table walk. If the memory micro-instruction causing the miss is a speculative micro-instruction, the page miss handler initiates a speculative page table walk. While performing the speculative page table walk, the page miss handler determines whether page table memory accessed during the page table walk is speculateable or non-speculateable memory. If non-speculateable, the speculative page table walk is aborted. A micro-instruction assisted page table walk is performed whenever access or dirty bits must be set for the pages accessed in the page table walk.

Method and apparatus for performing page table walks in a microprocessor

The write-combining buffer combines data from separate data write operations into cache-line-sized buffer units for uncacheable types of data, such as frame buffer data. The write-combining buffer is implemented within a microprocessor having a data cache unit storing cacheable data within cache-lines. The data cache unit includes components and circuitry provided for efficiently inputting and outputting cache-line-sized units of data. By combining many uncacheable data write operations within a single cache-line-sized buffer, the circuitry and techniques employed for processing cache-lines are exploited in the processing of uncacheable data as well. A particular implementation is described wherein uncacheable data units corresponding to graphics write operations within an out-of-order microprocessor are combined into cache-line-sized buffers, then transmitted to a frame buffer using a burst mode eviction. Processor ordering requirements are ignored and global observability is relaxed for the graphics write operations. If the cache line sized buffer is not full when evicted, then a sequence of one or more burst-mode partial writes are employed to evict all data within the cache line sized buffer. If partial writes are employed, no delay between the partial writes is required.

Method and apparatus for combining uncacheable write data into

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Hillsboro, OR, United States of America

Andy Glew