Infineon Technologies Ag

International Business Machines Corporation

Other

Infineon Technologies North America Corp.

Andy Cowley

Erdem Kaltalioglu

Mark Hoinkis

Timothy Joseph Dalton

Chih-Chao Yang

Kaushik Arun Kumar

Douglas C La Tulipe, Jr

Jochen Schacht

Andrew Herbert Simon

Larry Clevenger

Gerald R Friese

Michael Stetter

Lawrence Alfred Clevenger

Matthias Hierlemann

Markus Naujok

Steffen K Kaldor

Mohammed Fazil Fayaz

Dennis J Warner

Yun Yu Wang

Christopher Vincent Jahnes

Terry Allen Spooner

William Thomas Motsiff

Stephen Edward Greco

Kaushik Chanda

Sunfei Fang

Sun-Oo Kim

Yi-Hsiung Lin

Matthias P Hierlemann

Erdum Kaltalioglu

Peter Emmi

A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer.

Method and apparatus of stress relief in semiconductor structures

A metal hardmask for use with a Dual Damascene process used in the manufacturing of semiconductor devices. The metal hardmask has advantageous translucent characteristics to facilitate alignment between levels while fabricating a semiconductor device and avoids the formation of metal oxide residue deposits. The metal hardmask comprises a first or primary layer of TiN (titanium nitride) and a second or capping layer of TaN (tantalum nitride).

Bilayered metal hardmasks for use in dual damascene etch schemes

A dual damascene structure and method of fabrication thereof. An insulating layer comprises a first dielectric material and a second dielectric material, the second dielectric material being different from the first dielectric material. First conductive regions having a first pattern are formed in the first dielectric material, and second conductive regions having a second pattern are formed in the second dielectric material, the second pattern being different from the first pattern. One of the first dielectric material and the second dielectric material comprises an organic material, and the other dielectric material comprises an inorganic material. One of the first and second dielectric materials is etchable selective to the other dielectric material. A method of cleaning a semiconductor wafer processing chamber while a wafer remains residing within the chamber is also disclosed.

Dual damascene structure and method

Interconnect layers on a semiconductor body containing logic circuits (microprocessors, Asics or others) or random access memory cells (DRAMS) are formed in a manner to significantly reduce the number of shorts between adjacent conductor/vias with narrow separations in technologies having feature sizes of 0.18 microns or smaller. This is accomplished by etching to form recessed copper top surfaces on each layer after a chemical-mechanical polishing process has been completed. The thickness of an applied barrier layer, on the recessed copper surfaces, is controlled to become essentially co-planar with the surrounding insulator surfaces. A thicker barrier layer eliminates the need for a capping layer. The elimination of a capping layer results in a reduction in the overall capacitive coupling, stress, and cost.

Reduction of the shear stress in copper via's in organic interlayer dielectric material

Bilayered metal hardmasks for use in Dual Damascene etch schemes

A method of forming a composite intermetal dielectric structure is provided. An initial intermetal dielectric structure is provided, which includes a first dielectric layer and two conducting lines. The two conducting lines are located in the first dielectric layer. A portion of the first dielectric layer is removed between the conducting lines to form a trench. The trench is filled with a second dielectric material. The second dielectric material is a low-k dielectric having a dielectric constant less than that of the first dielectric layer.

Composite intermetal dielectric structure including low-k dielectric material

The act of blowing an unpassivated electrical fuse (for example, fuse) using a laser can result in the splattering of the fuse material and result in electrical short circuits. A blast barrier (for example blast barrier) formed around an area of the fuse that is blown by the laser helps to contain the splattering of the fuse material. The blast barrier may be formed from the same material as the fuses themselves and, therefore, can be created in the same fabrication step.

Reduced splattering of unpassivated laser fuses

Thermo-mechanical stress on vias is reduced, thereby reducing related failures. This can be done by maintaining a via-to-metal area ratio at least as large as a predetermined value below which the additional stress on the vias does not significantly increase.

Via density rules

A conductive line is formed in a first insulating layer. A second insulating layer is formed over the conductive line and the first insulating layer. A via extends through the second insulating layer to contact at least the top surface of the conductive line. The via also extends through the first insulating layer to contact at least a top portion of at least one sidewall of the conductive line. The conductive line sidewall may include an outwardly extending hook region, so that a portion of the via is disposed beneath the conductive line hook region, forming a locking region within the via proximate the conductive line hook region.

Robust via structure and method

A method of fabricating a semiconductor device having a dielectric structure on which an interconnect structure is optionally patterned using lithographic and etching techniques, within a single deposition chamber, is provided. The dielectric structure may optionally be covered by diffusion barrier materials prior to a sputter etching process. This sputter etching process is used to remove the native oxide on an underneath metal conductor surface and includes a directional gaseous bombardment with simultaneous deposition of metal neutral. Diffusion barrier materials may also be deposited into the pattern.

Simultaneous native oxide removal and metal neutral deposition method

Plasma RIE polymer removal

Dual hardmask single damascene integration scheme in an organic low k ILD

Growing community of inventors

Wappingers Falls, NY, United States of America

Andy Cowley