Fujitsu Corporation

Andy Cheung

Kazuhiro Kurihara

Yasushi Kasa

Tsutomu Nakai

Yoshihiro Tsukidate

Yasushi Oka

A semiconductor memory device includes a plurality of blocks, each of which includes a memory cell array, and outputs data signals and a redundancy signal. The semiconductor memory device further includes at least one first multiplexer which is coupled to the blocks, and selects one of the blocks, and a second multiplexer which performs redundancy processing based on the data signals and the redundancy signal which have undergone block selection by the first multiplexer.

Semiconductor memory device with memory cell array divided into blocks

A memory circuit has a plurality of blocks which further comprises a plurality of regular sectors and a spare sector, wherein each sector further comprises a plurality of memory cells, and when a regular sector in a first block is defective, this defective regular sector is replaced with a spare sector in a second block. And responding to an address to be supplied, the regular sector corresponding to the supplied address in the first block and the spare selector in the second block are selected simultaneously during a first period, and after the first period, selection of one of the regular sector and the spare sector is maintained according to the result of redundancy judgment on whether the supply address matches with the redundant address. Regardless the result of redundancy judgment on whether the supplied address matches the redundant address indicating the defective sector, a regular sector in the first block and the spare sector in the second block, to be a pair thereof, are set to selected status simultaneously during the first period when access operation stars, so a drop in access speed due to a redundancy judgment operation can be suppressed.

Memory circuit with redundant configuration

A semiconductor memory includes a core array including a plurality of memory cells, and a redundant array to be substituted for a substitution object area having a defective cell in the core array. In this semiconductor memory, there are provided a substitution address memory which stores an address of a first substitution object area including both sides of the defective cell as a substitution object address, and a redundancy controller which controls to substitute the redundant array for the substitution object area of the core array. When a portion of the first substitution object area is located on the outside of the core array, the redundancy controller controls to substitute the redundant array for a second substitution object area which has the defective cell and is located on the inside of the core array.

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Kawasaki, Japan

Andy Cheung