Advanced Micro Devices Corporation

Globalfoundries Inc.

Andy C Wei

Jan Hoentschel

Thorsten E Kammler

Manfred Horstmann

Andreas Gehring

Thilo Scheiper

Mark Brandon Fuselier

Derick J Wristers

Markus Lenski

Roman Boschke

Anthony Mowry

Casey Scott

Peter Baars

Ralf Richter

Sven Beyer

Andrew Michael Waite

Peter Javorka

Uwe Griebenow

Maciej Wiatr

Jagar Singh

Jens Heinrich

Richard Carter

Vassilios Papageorgiou

Klaus Hempel

Robert Mulfinger

Stefan Flachowsky

Guillaume Bouche

Mahadeva Iyer Natarajan

Frank Wirbeleit

Andreas Kurz

Gunter Grasshoff

Andreas Ott

Michael Raab

Johannes F Groschopf

Joe Bloomquist

Stephan Kronholz

Jason Eugene Stephens

Martin Trentzsch

Igor V Peidous

Martin Mazur

Gert Burbach

Karla Romero

Markus Forsberg

Erik P Geiss

Shyam Pal

Ina Ostermay

Till Schloesser

Jinping Liu

Huang Liu

Scott D Luning

Haigou Huang

Witold P Maszara

James F Buller

Thomas Werner

Rohit Pal

David Donggang Wu

Roderick Alan Augur

Manjunatha Govinda Prabhu

Matthias Schaller

Xiang Hu

David C Pritchard

Akif Sultan

Joerg Hohage

Mario M Pelella

Frank Jakubowski

Ralf Illgen

Ralf Van Bentum

Christoph Schwan

Huy Cao

Xintuo Dai

Martin Gerhardt

Linus Jang

Bharat V Krishnan

Tom Herrmann

Manuj Rathor

Tuhin Guha Neogi

Akshey Sehgal

Mark Alexander Zaleski

Craig Child

Deniz Elizabeth Civay

Frank Seliger

Robert Binder

Heike Salz

Anil Kumar

Haifeng Sheng

Wolfgang Buchholtz

Ping-Chin Yeh

Joachim Metzger

Chang Ho Maeng

Kai Sun

Vivien Schroeder

Tim Baldauf

Erik Geiss

David Michael Permana

Frank Ludwig

Fernando Koch

David C Greenlaw

Andreas Hellmich

Kenneth Andrew Bates

Katja Steffen

Semiconductor devices and methods of fabricating the semiconductor devices with cross coupled contacts using patterning for cross couple pick-up are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a first lithography to pattern a first shape; performing a second lithography to pattern a second shape overlapping a portion of the first shape; processing the first shape and the second shape to form an isolation region at the overlap; and forming four regions separated by the isolation region. An intermediate semiconductor device is also disclosed.

Devices and methods for forming cross coupled contacts

Semiconductor devices and methods of fabricating the semiconductor devices with chamfer-less via multi-patterning are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a trench etch into a portion of the intermediate semiconductor device to form a trench pattern; depositing an etching stack; performing at least one via patterning process; and forming at least one via opening into a portion of the intermediate semiconductor device. An intermediate semiconductor device is also disclosed.

Devices with chamfer-less vias multi-patterning and methods for forming chamfer-less vias

Methods of MOL S/D contact patterning of RMG devices without gouging of the Rx area or replacement of the dielectric are provided. Embodiments include forming a SOG layer around a RMG structure, the RMG structure having a contact etch stop layer and a gate cap layer; forming a lithography stack over the SOG and gate cap layers; patterning first and second TS openings through the lithography stack down to the SOG layer; removing a portion of the SOG layer through the first and second TS openings, the removing selective to the contact etch stop layer; converting the SOG layer to a SiOlayer; forming a metal layer over the SiOlayer; and planarizing the metal and SiOlayers down to the gate cap layer.

Siloxane and organic-based MOL contact patterning

By forming a trench isolation structure after providing a high-k dielectric layer stack, direct contact of oxygen-containing insulating material of a top surface of the trench isolation structure with the high-k dielectric material in shared polylines may be avoided. This technique is self-aligned, thereby enabling further device scaling without requiring very tight lithography tolerances. After forming the trench isolation structure, the desired electrical connection across the trench isolation structure may be re-established by providing a further conductive material.

Semiconductor device having a high-K gate dielectric above an STI region

Three-dimensional electrostatic discharge (ESD) semiconductor devices are fabricated together with three-dimensional non-ESD semiconductor devices. For example, an ESD diode and FinFET are fabricated on the same bulk semiconductor substrate. A spacer merger technique is used in the ESD portion of a substrate to create double-width fins on which the ESD devices can be made larger to handle more current.

Three-dimensional electrostatic discharge semiconductor device

There is set forth herein a field effect transistor (FET) configured as an ESD protection device. In one embodiment, the FET can be configured to operate in a snapback operating mode. The FET can include a semiconductor substrate, a gate formed on the substrate and a dummy gate formed on the substrate spaced apart from the gate.

ESD snapback based clamp for finFET

In sophisticated semiconductor devices, an asymmetric transistor configuration may be obtained on the basis of an asymmetric well implantation while avoiding a tilted implantation process. For this purpose, a graded implantation mask may be formed, such as a graded resist mask, which may have a higher ion blocking capability at the drain side compared to the source side of the asymmetric transistor. For instance, the asymmetric configuration may be obtained on the basis of a non-tilted implantation process with a high degree of performance gain and may be accomplished irrespective of the technology standard under consideration.

Graded well implantation for asymmetric transistors having reduced gate electrode pitches

By reconfiguring material in a recess formed in drain and source regions of SOI transistors, the depth of the recess may be increased down to the buried insulating layer prior to forming respective metal silicide regions, thereby reducing series resistance and enhancing the stress transfer when the corresponding transistor element is covered by a highly stressed dielectric material. The material redistribution may be accomplished on the basis of a high temperature hydrogen bake.

SOI transistor having drain and source regions of reduced length and a stressed dielectric material adjacent thereto

A method of forming a metal gate diode ESD protection device and the resulting device are provided. Embodiments include forming a metal gate diode including a metal gate on a substrate; forming an n-type cathode on a first side of the metal gate diode; and forming a p-type anode on a second side of the metal gate diode, opposite the first side.

Metal gate for robust ESD protection

In sophisticated semiconductor devices, the contact structure may be formed on the basis of contact bars formed in a lower portion of an interlayer dielectric material, which may then be contacted by contact elements having reduced lateral dimensions so as to preserve a desired low overall fringing capacitance. The concept of contact bars of reduced height level may be efficiently combined with sophisticated replacement gate approaches.

Contact bars with reduced fringing capacitance in a semiconductor device

Methods are provided for fabricating integrated circuits. One method includes etching a plurality of trenches into a silicon substrate and filling the trenches with an insulating material to delineate a plurality of spaced apart silicon fins. A layer of undoped silicon is epitaxially grown to form an upper, undoped region of the fins. Dummy gate structures are formed overlying and transverse to the plurality of fins and a back fill material fills between the dummy gate structures. The dummy gate structures are removed to expose a portion of the fins and a high-k dielectric material and a work function determining gate electrode material are deposited overlying the portion of the fins. The back fill material is removed to expose a second portion and metal silicide contacts are formed on the second portion. Conductive contacts are then formed to the work function determining material and to the metal silicide.

Methods for fabricating integrated circuits

In a replacement gate approach, the exposure of the placeholder material of the gate electrode structures may be accomplished on the basis of an etch process, thereby avoiding the introduction of process-related non-uniformities, which are typically associated with a complex polishing process for exposing the top surface of the placeholder material. In some illustrative embodiments, the placeholder material may be exposed by an etch process based on a sacrificial mask material.

Replacement gate approach for high-k metal gate stacks by avoiding a polishing process for exposing the placeholder material

Method for self-aligned removal of a high-K gate dielectric above an STI region

An embedded or buried resistive structure may be formed by amorphizing a semiconductor material and subsequently re-crystallizing the same in a polycrystalline state, thereby providing a high degree of compatibility with conventional polycrystalline resistors, such as polysilicon resistors, while avoiding the deposition of a dedicated polycrystalline material. Hence, polycrystalline resistors may be advantageously combined with sophisticated transistor architectures based on non-silicon gate electrode materials, while also providing high performance of the resistors with respect to the parasitic capacitance.

Semiconductor device comprising a buried poly resistor

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Radebeul/Dresden, Germany

Andy C Wei