Dell Products Inc.

Andy Butcher

Wei G Liu

Mark W Shutt

Quy Hoang

Lee Eric Ballard

An information handling system includes a processor and NIC coupled to the processor via a communication interface. The NIC includes a network port. The processor instantiates a virtual network including at least two virtual switches and a virtual machine. The NIC receives a first flow from a first virtual switch, the first flow directing data packets received on the network port and destined for the virtual machine to a second virtual switch, and receives a second flow from the second virtual switch, the second flow directing the data packets to the virtual machine. The NIC further receives a data packet on the network port, determines that the data packet is destined for the virtual machine, and routes the data packet to a virtual function associated with the virtual machine based on the first and second flows, without first routing the first data packet to either of the virtual switches.

System and method for hardware offloading of nested virtual switches

An information handling system includes a dual in-line memory module (DIMM) coupled to a memory controller via a memory channel. A processor during a first in time boot process of the information handling system determines a first environmental condition of the information handling system, and initializes the memory controller and the DIMM to determine a first set of initialization parameters for the memory controller and the DIMM. During a second in time boot process of the information handling system, the processor determines if a second environmental condition is different than the first environmental condition, if the second environmental condition is not different then to continue the second in time boot process without initializing the memory controller and the DIMM, and if the second environmental condition is different then to initialize the memory controller and the DIMM to determine a second set of initialization parameters for the memory controller and the DIMM.

Dual inline memory module with multiple boot processes based on first and second environmental conditions

An information handling system includes a dual in-line memory module (DIMM) coupled to a memory controller. The memory controller provides interrupts to a processor each time a read transaction from the DIMM results in a correctable read error. The processor instantiates a failure predictor that receives the interrupts, accumulates a count of the interrupts, and provides an error indication when the count exceeds an error threshold. In accumulating the count, the failure predictor increments the count each time the predictor receives a particular interrupt and decrements the count in accordance with an error leak rate. The error leak rate has a first value when a training coefficient for the DIMM is greater than a deviation threshold, and has a second value when the training coefficient for the DIMM is less than the deviation threshold.

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Cedar Park, TX, United States of America

Andy Butcher