Elmos Semiconductor Se

André Srowig

Fabian Finkeldey

Marco Liem

Bernold Rix

A laser module comprises a plurality of laser submodules with a respective plurality of lasers. Each laser submodule has a driver IC. Each driver IC controls several lasers. The driver ICs of the laser module can use the received signals of photodetectors to homogenize and readjust the real emission amplitude of the laser pulses for all lasers of the laser module and regulate the emission point in time of the respective real laser pulses to a synchronization signal. The driver IC can detect a failure of a laser by the photodetector belonging to it and output an error signal. The lasers directly coupled with the photodetectors in a compact design.

Mechanically free LIDAR system

A lidar receiver circuit for receiving optical signals using photodetectors to detect events or objects in the surrounding area, with a redundancy of receiver circuits for reducing failure probability, including a photodetector array for receiving optical signals and outputting a measurement signal, wherein the photodetectors are arranged as a two-dimensional matrix, a plurality of receiver circuits for receiving the measurement signal; a plurality of multiplexers, which are electrically arranged between the array and circuits and are connected thereto; wherein at least one of the multiplexers is connected to a column of photodetectors and at least two receiver circuits; each circuit is configured to receive and process the measurement signals of a column; a column of photodetectors is assigned to each receiver circuit by default; and the multiplexers connect a column to a receiver circuit other than the receiver circuit, which is assigned to the column of photodetectors by default.

Lidar receiver circuit having redundancy to bypass failure

A timing generator as master clock for an electronic circuit includes a coarse code and a plurality of fine codes, has a ring oscillator with an uneven number n of delay elements, each of which has a delay output at which clock signal is present; clock dividers which are connected to the delay outputs and at whose output a clock divider output signal is output; start circuit for generating initialization signal to trigger clock dividers, and clock generator that further processes clock signal and generates a coarse code, and an output at which generated timestamp is output, wherein the fine codes of timestamp are formed from clock divider output signals of the clock dividers, and the coarse code and the fine codes contain redundant information that a time shift of the fine codes relative to the coarse code by at most (n&#x2212;1)/2 time differences results in a correct timestamp.

Timing generator as master clock for an electronic circuit

The device executes a method for determining the delay time of a first wavelet in a transmission path (I). For this purpose, the first wavelet is transmitted into the transmission path (I) at a time after a reference time. After passing through the transmission path (I), the delayed and typically deformed transmission wavelet is scalar-multiplied with a second (analysis) wavelet. The result is compared to a reference value. The scalar product value adopts the reference value at a time (t). The delay of the first and/or second wavelet in relation to the reference time is adjusted according to said time (t) in relation to the reference time. An amplitude adjustment is not carried out.

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Heidelberg, Germany

André Srowig