Intel Corporation

Andrey Rodchenko

Dmitry M Maslennikov

Andrey Chudnovets

Sergey P Scherbinin

Marat Zakirov

Boris V Shurygin

Yevgeniy M Astigeyevich

Pavel G Matveyev

Methods, apparatus, systems, and articles of manufacture to compile instructions for a vector of instruction pointers (VIP) processor architecture are disclosed. An example method includes identifying a strand including a fork instruction introducing a first speculative assumption. A basing instruction to initialize a basing value of the strand before execution of a first instruction under the first speculative assumption. A determination of whether a second instruction under a second speculative assumption modifies a first memory address that is also modified by the first instruction under the first speculative assumption is made. The second instruction is not modified when the second instruction does not modify the first memory address. The second instruction is modified based on the basing value when the second instruction modifies the first memory address, the basing value to cause the second instruction to modify a second memory address different from the first memory address.

Methods and apparatus to compile instructions for a vector of instruction pointers processor architecture to enable speculative execution and avoid data corruption

Methods, apparatus, systems, and articles of manufacture to compile instructions for a vector of instruction pointers (VIP) processor architecture are disclosed. An example method includes identifying a predicate dependency between a first compiled instruction and a second compiled instruction at a control flow join point, the second compiled instruction having different speculative assumptions corresponding to how the second compiled instruction will be executed based on an outcome of the first compiled instruction. A first strand is organized to execute a first instance of the second compiled instruction corresponding to a first one of the speculative assumptions, and a second strand to execute a second instance of the second compiled instruction corresponding to a second one of the speculative assumptions which is opposite to the first one of the speculative assumptions. The first instance of the second compiled instruction and the second instance of the second compiled instruction are executed in an asynchronous manner relative to each other and to the first compiled instruction.

Methods and apparatus to compile instructions for a vector of instruction pointers processor architecture

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Moscow, Russia

Andrey Rodchenko