Motorola Corporation

Andrey P Plis

Alexander Mikhailovich Marchenko

Mikhail Anatolievich Sotnikov

Patrick James McGuinness

Gopal Vijayan

Eugene G Shiro

Patrick McGuiness

Igor Topouzov

Vijayan Gopalakrishnan

A channel routing method ( ) comprises computing channel parameters ( ), classifying a channel complexity and estimating a channel height ( ), optionally, determining a trunk placement direction ( ), assigning tracks and layers ( ), determining a quality function QF ( ), and optimizing ( ). The channel complexity is classified using predetermined weighting parameters (a to a ). This classification selects a significance vector n. In the assigning step ( ), the vector n is combined with the channel parameters to a criterion. The criterion is used the select the most suitable assignment. In repetitions of assigning, determining QF and optimizing steps, the significance vector n and, optionally, QF are modified. The repetition are stopped upon compliance of a breaking condition which can refer to QF.

Method for channel routing, and apparatus

The invention concerns a method for manufacturing an electronic device having a channel. The channel has a number of rows and columns for wiring of nets. Usually each wiring layer is dedicated to either the rows or the columns. According to this method certain row segments can be shifted from one wiring layer to another, so that the channel area is used more effectively.

Method and apparatus for channel-routing of an electronic device

The invention relates to a method for manufacturing of electronic devices, such as very large scale integrated devices, having a channel. The channel routing is done based on a compositional approach in which initially all individual terminals are represented by individual nodes in a terminal vertical constraint graph. Individual constraints between individual terminals are represented by separate edges. This approach allows the resolution of difficult classes of routing problems in an efficient way.

Method for manufacturing and designing a wiring of a channel of an electronic device and electronic apparatus

In an improved routing method vertical constraint graph is generated in which a critical node is selected. The critical node is expanded to contain corresponding terminals. The resulting subnodes within the critical node are interconnected by edges that are representative of vertical constraints. A graph coloring method is employed to split the critical node into a number of new nodes. Thereby it is possible to route channels having multi-dimensional vertical constrains.

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Moscow, Russia

Andrey P Plis