X-fab Semiconductor Foundries Gmbh

Andrey Hudyryev

Soeren Lohbrandt

Predrag Micakovic

Holger Haberla

A flash memory comprising a first plurality of memory cells, each memory cell of the first plurality of memory cells selectively connected to a first input of a comparator. A second plurality of memory cells selectively connected to a second input of the comparator, wherein a first number of the second plurality of memory cells are in an erased state, wherein a second number of the second plurality of memory cells are in a written state, wherein each memory cell of the first plurality of memory cells and each memory cell of the second plurality of memory cells has a first cell capacitance, and wherein the sum of the first number and the second number is at least three.

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Bad Berka, Germany

Andrey Hudyryev