Adeia Semiconductor Bonding Technologies Inc.

Flir Systems, Incorporated

Tessera Technologies Ireland Limited

Tessera Technologies Hungary Kft.

Andrey Grinman

David Ovrutsky

Vage Oganesian

Charles Rosenstein

Belgacem Haba

Giles Humpston

Osher Avsian

Hagit Gershtenman-Avsian

Alexander Feldman

Felix Hazanovich

Yulia Aksenton

Avi Dayan

Ilya Hecht

Alan D Kathman

Moti Margalit

Michael James Nystrom

Robert Burtzlaff

Mitchell Hayes Reifel

An optoelectronic device package includes an optoelectronic device having an active region on a first surface of a substrate, a bond pad area on the first surface that includes at least one contact pad electrically connected to the active region, and a cap having a first cap surface and a second cap surface, the first cap surface being secured to the first surface of the substrate, the cap covering the optoelectronic device. At least one of the cap and the substrate has an angled sidewall extending at an angle relative to an axis parallel to an optical path. The at least one contact pad is exposed by and adjacent to the angled sidewall. An electrical line extends from each of the at least one contact pad along the angled sidewall and to the second cap surface that does not overlap the active region.

Methods for routing electrical interconnections and resultant structures

A method of singulating includes scribing a first scribe line on a first side of a substrate, scribing a second scribe line on a second side of the substrate, the first and second sides facing away from each other, the second scribe line being substantially parallel to the first scribe line, and simultaneously separating the substrate at the first scribe line and the second scribe line.

Methods for singulation and packaging

A chip-sized, wafer level packaged device including a portion of a semiconductor wafer including a device, at least one packaging layer containing silicon and formed over the device, a first ball grid array formed over a surface of the at least one packaging layer and being electrically connected to the device and a second ball grid array formed over a surface of the portion of the semiconductor wafer and being electrically connected to the device.

Packaged semiconductor chips with array

A chip-sized wafer level packaged device including a portion of a semiconductor wafer including a device, a packaging layer formed over the portion of the semiconductor wafer, the packaging layer including a material having thermal expansion characteristics similar to those of the semiconductor wafer and a ball grid array formed over a surface of the packaging layer and being electrically connected to the device.

Packaged semiconductor chips

A stacked microelectronic unit is provided which has a top surface and a bottom surface remote from the top surface and a plurality of vertically stacked microelectronic elements therein, including at least one microelectronic element having a front face adjacent to the top surface and a rear face oriented towards the bottom surface. Each of the microelectronic elements has traces extending from contacts at the front face beyond edges of the microelectronic element. A dielectric layer contacts edges of the microelectronic elements and underlies the rear face of the at least one microelectronic element. Leads are connected to the traces extending along the dielectric layer. Unit contacts, exposed at the top surface, are connected to the leads.

Stack packages using reconstituted wafers

Packaged microelectronic elements are provided. In an exemplary embodiment, a microelectronic element having a front face and a plurality of peripheral edges bounding the front face has a device region at the front face and a contact region with a plurality of exposed contacts adjacent to at least one of the peripheral edges. The packaged element may include a plurality of support walls overlying the front face of the microelectronic element such that a lid can be mounted to the support walls above the microelectronic element. For example, the lid may have an inner surface confronting the front face. In a particular embodiment, some of the contacts can be exposed beyond edges of the lid.

Wafer level chip packaging

A method is provided for fabricating a unit including a semiconductor element such as a sensor unit, e.g., for optical imaging. A semiconductor element has plurality of conductive features exposed at the front surface and semiconductive or conductive material exposed at at least one of the front and rear surfaces. At least some of the conductive features are insulated from the exposed semiconductive or conductive material. By electrodeposition, an insulative layer is formed to overlie the at least one of exposed semiconductive material or conductive material. Subsequently, a plurality of conductive contacts and a plurality of conductive traces are formed overlying the electrodeposited insulative layer, the conductive traces connecting the conductive features to the conductive contacts on the rear surface. The unit can be incorporated in a camera module having an optical element in registration with an imaging area of the semiconductor element.

Wafer-level fabrication of lidded chips with electrodeposited dielectric coating

Growing community of inventors

Jerusalem, Israel

Andrey Grinman