Intel Corporation

Andrey Efimov

Andrey Vladimirovich Belogolovy

Vladislav A Chernyshev

Evguenii Avramovich Krouk

Mikhail Yurievich Lyakh

Boris A Babayan

Andrei Ovchinnikov

Sergey Y Shishlov

Felix Aleksandrovich Taubin

Andrey Kluchnikov

Grigory Sergeevich Evseev

Kamil Garifullin

Mikhail S Tsvetkov

Aliaksei Vladimirovich Chapyzhenka

Andrei Anatol'evich Ovchinnikov

Alexey Trofimenko

Ilya Vladimirovich Katsov

Igor Burovenko

Anton Lechanka

Evgeny Belyaev

Anton Lechenko

A processor includes logic to execute an instruction stream out-of-order. The instruction stream is divided into a plurality of strands and its instructions and those within the streams are ordered by program order (PO). The processor further includes logic to identify an oldest undispatched instruction in the instruction stream and record its associated PO as an executed instruction pointer, identify a most recently committed store instruction in the instruction stream and record its associated PO as a store commitment pointer, a search pointer with PO less than the execution instruction pointer, identify a first set of store instructions in a store buffer with PO less than the search pointer and eligible for commitment, evaluate whether the first set of store instructions is larger than a number of read ports of the store buffer, and adjust the search pointer.

Instruction and logic for sorting and retiring stores

A method and system may include an interface to receive a video signal and an encoder to compress the video signal on a per-slice basis. In one example, compression of the video signal involves the use () of a hash value and an allowable distortion of each slice to select () a quantization parameter for the slice. The selected quantization parameter can be used to encode () the slice. In addition, a processor can manage wireless transmission of the compressed video signal.

Wireless display encoder architecture

Embodiments of a space-time decoder and methods for decoding Alamouti-encoded signals in high-Doppler environments are generally described herein. Other embodiments may be described and claimed. In some embodiments, soft-symbol outputs are generated from received symbols, a channel rate-of-change, and channel coefficients. Maximum-likelihood decoding may be performed to generate hard-symbol outputs from the soft-symbol outputs.

Space-time decoder and methods for decoding alamouti-encoded signals in high-doppler environments

Apparatus and methods are provided to decode signals from a communication channel to reconstruct transmitted information. Embodiments may include applying a plurality of decoders to a code, in which reliability values are provided to a decoder such that the decoder receives the reliability values determined by and provided from only one other decoder of the plurality of decoders. A valid codeword may be output from application of the plurality of decoders to the code.

Modified turbo-decoding message-passing algorithm for low-density parity check codes

Methods, apparatus, and systems are provided to encode a low-density parity-check codeword for transmission in a communications channel. In an embodiment, the encoding may include partially computing parity-check bits in response to receiving a block of message bits before obtaining all the message bits for the low-density parity-check codeword, including updating previously partially computed parity-check bits that depend on the received block.

Fast low-density parity-check code encoder

Apparatus and methods are provided to correct burst errors from a communication channel. Embodiments may include correcting burst errors in received data using a decoder configured as a Meggitt decoder with an additional selection criterion to correct a burst error having a length larger than the code error correction capability.

Modification to Meggitt decoder for burst error correction codes

A unified decoder is capable of decoding data encoded with convolutional codes, Turbo codes, and LDPC codes. In at least one embodiment, a unified decoder is implemented within a multi-standard wireless device.

Unified decoder for convolutional, turbo, and LDPC codes

An integrated incremental redundancy symbol mapping diversity system for a communication device. The integrated incremental redundancy symbol mapping diversity system includes a transmitter. The transmitter packetizes a retransmission packet according to a modulation scheme in response to a retransmission request from the receiver. The transmitter includes an output packet processor and an inter-packet selective symbol mapper. The output packet processor determines a transmission iteration of a bit segment of the retransmission packet. The inter-packet selective symbol mapper applies a first symbol map pattern to the bit segment based on the transmission iteration of the bit segment and applies a second symbol map pattern to another bit segment of the retransmission packet based on the transmission iteration of the other bit segment. The first symbol map pattern is different from the second symbol map pattern.

Inter-packet selective symbol mapping in a joint incremental redundancy and symbol mapping diversity system

A method and apparatus are provided for error correction of a communication signal. A multiple fixed threshold scheme for iteratively decoding a received codeword includes making a comparison with a threshold to generate a reconstructed version of the received codeword. The threshold has at least two different values that at used during different iterations. The values of the threshold are fixed having been determined prior to decoding. In an embodiment, the fixed thresholds may be based on values for channel parameters and may be selected by a decoder that receives information regarding the channel parameter from a channel estimation unit monitoring the communication channel. Embodiments include decoding methods and apparatus using a threshold having two of more fixed values during the iterative decoding.

Channel estimation and fixed thresholds for multi-threshold decoding of low-density parity check codes

Methods and apparatus are provided for prescribed response precoding schemes for signal transmission in channels with intersymbol interference. An embodiment includes generating a prescribed feedback filter polynomial as the quotient of a feedback filter polynomial and a target polynomial to form a feedback filter in a precoder, where the target polynomial is a divisor of the feedback filter polynomial.

Prescribed response precoding for channels with intersymbol interference

Described herein are one or more implementations of a high-throughput and memory-efficient 'windowed' bidirectional Soft Output Viterbi Algorithm (BI-SOVA) decoder. The described BI-SOVA decoder uses the 'window' technique to concurrently decode several different non-overlapping portions of a subject signal in parallel.

High-throughput memory-efficient BI-SOVA decoder architecture

An embodiment of a decoder comprises processing elements operating on associative processing. The processing elements may comprise a logic and memory element. Each row of the decoder comprises one or more associative processing elements controlled by a row control element to determine the two minimum values. Each column comprises one or more associative processing elements, an input processing element, and a column control element to determine hard decision bits. The usage of processing elements to construct a decoder may reduce the gate count and decrease the interconnects used to couple the elements.

Low density parity check (LDPC) code decoder

A technique to perform fast decoding of a Reed-Solomon code. A first multiplier unit multiplies a matrix Bwith a column vector v using common adders to produce a column vector v. The vector v represents one of an error locator polynomial, an error evaluator polynomial, and a derivative polynomial for a (n, k) Reed-Solomon code. The matrix Bis over GF() including first h columns of a matrix B. A second multiplier unit multiplies non-unity components of a column vector A with non-zero components of the column vector vcomponent-wise in GF(q) to produce a column vector v, q being equal to n+1. A third multiplier unit multiplies diagonal sub-matrices of a matrix C with corresponding components of the column vector vin GF() to produce a column vector v

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St. Petersburg, Russia

Andrey Efimov