Samsung Electronics Co., Ltd.

Foundry Networks, Inc.

Andrew Zhenwen Chang

Ronak Patel

Ming G Wong

Krishna Teja Malladi

Yu-Mei Lin

Yuen Fai Wong

Yang Seok Ki

Ehsan M Najafabadi

Hongzhong Zheng

Sung Su Park

Ming Fung Wong

Vincent Tung Pham

Shiyu Li

Jong Won Park

Sun Young Kim

Yoon Jun Lee

Dongyan Jiang

Joo Hwan Lee

Praveen Krishnamoorthy

Chang Won Ryu

Jaemin Jung

Yong Joo Park

Soo Hyun Jho

Young Hoon Eom

Yiqun Zhang

Changho Choi

Hui Zhang

Jongmin Gim

Byung Choi

Wenqin Huangfu

Qiang Peng

Armin Haj Aboutalebi

Xiaodong Zhao

Vinit Sadanand Apte

Jingchi Yang

Mu Tien Chang

Brian Luu

Yukui Luo

Ehsan Najafabadi

Seo Gyun Kim

Byunghee Choi

A memory system is disclosed. The memory system may include a first cache-coherent interconnect memory module and a second cache-coherent interconnect memory module. A cache-coherent interconnect switch may connect the first cache-coherent interconnect memory module, the second cache-coherent interconnect memory module, and a processor. A processing element may process a data stored on at least one of the first cache-coherent interconnect memory module and the second cache-coherent interconnect memory module.

Cache-coherent interconnect based near-data-processing accelerator

Provided are systems, methods, and apparatuses for providing a storage resource. The method can include: operating a first controller coupled to a network interface in accordance with a cache coherent protocol; performing at least one operation on data associated with a cache using a second controller coupled to the first controller and coupled to a first memory; and storing the data on a second memory coupled to one of the first controller or the second controller.

Systems and methods for scalable and coherent memory devices

A coherent memory system. In some embodiments, the coherent memory system includes a first memory device. The first memory device may include a cache coherent controller; a volatile memory controller; a volatile memory; a nonvolatile memory controller; and a nonvolatile memory. The first memory device may be configured to receive a quality of service requirement and to selectively enable a first feature in response to the quality of service requirement.

Coherent memory system

A system for computing. In some embodiments, the system includes: a memory, the memory including one or more function-in-memory circuits; and a cache coherent protocol interface circuit having a first interface and a second interface. A function-in-memory circuit of the one or more function-in-memory circuits may be configured to perform an operation on operands including a first operand retrieved from the memory, to form a result. The first interface of the cache coherent protocol interface circuit may be connected to the memory, and the second interface of the cache coherent protocol interface circuit may be configured as a cache coherent protocol interface on a bus interface.

In-memory computing with cache coherent protocol

A system and method for training a neural network. In some embodiments, the system includes a computational storage device including a backing store. The computational storage device may be configured to: store, in the backing store, an embedding table for a neural network embedding operation; receive a first index vector including a first index and a second index; retrieve, from the backing store: a first row of the embedding table, corresponding to the first index, and a second row of the embedding table, corresponding to the second index; and calculate a first embedded vector based on the first row and the second row.

Neural network training with acceleration

An accelerator is disclosed. The accelerator may include an on-chip memory to store a data from a database. The on-chip memory may include a first memory bank and a second memory bank. The first memory bank may store the data, which may include a first value and a second value. A computational engine may execute, in parallel, a command on the first value in the data and the command on the second value in the data in the on-chip memory. The on-chip memory may be configured to load a second data from the database into the second memory bank in parallel with the computation engine executing the command on the first value in the data and executing the command on the second value in the data.

In-memory database (IMDB) acceleration through near data processing

A storage device is disclosed. The storage device may include a storage for a data and a controller to manage access to the data in the storage. A mechanism may automatically manage a bias mode for a chunk of the data in the storage, the bias mode including one of a host bias mode and a device bias mode.

Systems and methods for managing bias mode switching

A system and method for training a neural network. In some embodiments, the system includes: a graphics processing unit cluster; and a computational storage cluster connected to the graphics processing unit cluster by a cache-coherent system interconnect. The graphics processing unit cluster may include one or more graphics processing units. The computational storage cluster may include one or more computational storage devices. A first computational storage device of the one or more computational storage devices may be configured to (i) store an embedding table, (ii) receive an index vector including a first index and a second index; and (iii) calculate an embedded vector based on: a first row of the embedding table, corresponding to the first index, and a second row of the embedding table, corresponding to the second index.

A method includes receiving, at a hardware circuit of a device, a target value corresponding to a target data. The method further includes outputting, from the hardware circuit, a first indicator that source data corresponds to the target value. The method further includes, based on the first indicator, outputting, from software executing at the device, a result indicator that the source data corresponds to the target data.

Systems and methods for data comparison

A method of processing data may include receiving a stream of first keys associated with first data, receiving a stream of second keys associated with second data, comparing, in parallel, a batch of the first keys and a batch of the second keys, collecting one or more results from the comparing, and gathering one or more results from the collecting. The collecting may include reducing an index matrix and a mask matrix. Gathering one or more results may include storing, in a leftover vector, at least a portion of the one or more results from the collecting. Gathering one or more results further may include combining at least a portion of the leftover vector from a first cycle with at least a portion of the one or more results from the collecting from a second cycle.

Systems, methods, and devices for acceleration of merge join operations

Systems and methods for error detection for an address channel are disclosed. The method includes generating a token, applying the token to a request at a source, and generating a first result. The request with the first result is transmitted to a destination over the address channel. A determination is made, at the destination, whether an error associated with the request has occurred. The determining whether the error has occurred includes: receiving a received request corresponding to the request over the address channel; receiving the first result with the received request; applying the token to the received request and generating a second result; comparing the first result with the second result; and transmitting a signal in response to the comparing.

Systems and methods for detecting intra-chip communication errors in a reconfigurable hardware system

A method and a memory device are provided. Data is obtained for a scan operation at an input buffer of a scan kernel in the memory device. The input buffer is adaptable to a first mode and a second mode of the scan kernel. Preprocessing of the data from the input buffer is performed to generate preprocessed data. A different type of preprocessing is performed for the first mode and the second mode. The preprocessed data is filtered to generate a filtered result. The filtered result is provided from the scan kernel to a controller of the memory device.

Systems and methods for database scan acceleration

A system and method for managing memory resources. In some embodiments the system includes a first server, a second server, and a server-linking switch connected to the first server and to the second server. The first server may include a stored-program processing circuit, a cache-coherent switch, and a first memory module. In some embodiments, the first memory module is connected to the cache-coherent switch, the cache-coherent switch is connected to the server-linking switch, and the stored-program processing circuit is connected to the cache-coherent switch.

System with cache-coherent memory and server-linking switch

A method of processing data in a system having a host and a storage node may include performing a shuffle operation on data stored at the storage node, wherein the shuffle operation may include performing a shuffle write operation, and performing a shuffle read operation, wherein at least a portion of the shuffle operation is performed by an accelerator at the storage node. A method for partitioning data may include sampling, at a device, data from one or more partitions based on a number of samples, transferring the sampled data from the device to a host, determining, at the host, one or more splitters based on the sampled data, communicating the one or more splitters from the host to the device, and partitioning, at the device, data for the one or more partitions based on the one or more splitters.

Systems, methods, and devices for storage shuffle acceleration

Growing community of inventors

Los Altos, CA, United States of America

Andrew Zhenwen Chang