Intel Corporation

Andrew Y Sun

Sailesh Kottapalli

Udo Walterscheidt

Thomas Y Yeh

Kinkee Sit

Rahul Pal

Henk G Neefs

Manoj K Arora

Ravindra P Saraf

In one embodiment, the present invention includes a processor having at least one core and uncore logic. The uncore logic can include a home agent to act as a guard to control access to a memory region. Either in the home agent or another portion of the uncore logic, a directory cache may be provided to store ownership information for a portion of the memory region owned by an agent coupled to the processor. In this way, when an access request for the memory region misses in the directory cache, a memory transaction can be avoided. Other embodiments are described and claimed.

Providing a directory cache for peripheral devices

A method and apparatus for improving dispersal performance of instruction threads is described. In one embodiment, the dispersal logic determines whether the instructions supplied to it include any NOP instructions. When a NOP instruction is detected, the dispersal logic places the NOP into a no-op port for execution. All other instructions are distributed to the proper execution pipes in a normal manner. Because the NOP instructions do not use the execution resources of other instructions, all instruction threads can be executed in one cycle.

Method and apparatus for improving dispersal performance in a processor through the use of no-op ports

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Cupertino, CA, United States of America

Andrew Y Sun