Qualcomm Incorporated

Andrew Weil

Dongwon Seo

Ashok Swaminathan

Debesh Bhatta

Haibo Fei

John Abcarius

Jaswinder Singh

Shahin Mehdizad Taleie

Behnam Sedighi

Nitz Saputra

Siyu Yang

Gurkanwal Singh Sahota

Sameer Wadhwa

Jeffrey Mark Hinrichs

Xiaohong Quan

Karthik Nagarajan

Wenjing Yin

Kevin Jia-Nong Wang

Honghao Ji

Christian Venerus

Negar Rashidi

Xiahan Zhou

Zongyu Dong

Bo Pang

Xilin Liu

Matthew Chauncey Kusbit

Sudharsan Kanagaraj

Benjamin Griffitts

Robert Martin Ondris

Mahmoud Elhebeary

Sarthak Kalani

Techniques and apparatus for determining dynamic current mismatches in a current-steering digital-to-analog converter (DAC) are provided. One example technique generally includes accumulating current mismatches between a DAC cell of a plurality of DAC cells and a reference cell using a capacitive element and changing a polarity of the capacitive element during the accumulating. The timing of the accumulating may be controlled such that a static current mismatch between the DAC cell and the reference cell is at least reduced and a dynamic current mismatch between the DAC cell and the reference cell is enhanced.

Dynamic current mismatch accumulation schemes for digital-to-analog converters

A duty cycle correction circuit includes four pairs of serially coupled transistors. A first two of the serial pairs of transistors couple between an internal node for complement output clock signal and ground. A second two of the serial pairs of transistors couple between the internal node and a power supply node for a power supply voltage. Each serial pair is controlled by a corresponding pair of quadrature clock signals in which one of the quadrature clock signal is delayed with respect to the other quadrature clock signal be one quarter of a clock period. The first two serial pairs of transistors thus combine to discharge the internal node for one-half clock period whereas the second two serial pairs of transistors combine to charge the internal node for one-half clock period so that the complement output clock signal has a 50% duty cycle.

Quadrature duty cycle correction circuit

Certain aspects of the present disclosure are directed towards a digital-to-analog converter (DAC) system. The DAC system generally includes a first driver and a plurality of current-steering cells. A first current-steering cell of the plurality of current-steering cells includes: a first current source coupled to a first current-steering transistor and a second current-steering transistor, wherein a gate of the first current-steering transistor and a gate of the second current-steering transistor are coupled to a first output and a second output of the first driver, respectively; a first transistor having a source coupled to a current source path and a drain coupled to a reference potential node; and a second transistor having a source coupled to the current source path and a drain coupled to the reference potential node.

Load matching for a current-steering digital-to-analog converter

Certain aspects of the present disclosure generally relate to a digital-to-analog converter (DAC) circuit implemented with a dynamic stacked transistor architecture. The DAC circuit generally includes a first current-steering transistor and a second current-steering transistor. The DAC circuit may also include: a first stacked transistor coupled between the first current-steering transistor and a first output of the DAC circuit; a first switch coupled between a gate of the first stacked transistor and a bias voltage node; a second switch coupled between the gate of the first stacked transistor and a voltage rail; a second stacked transistor coupled between the second current-steering transistor and a second output of the DAC circuit; a third switch coupled between a gate of the second stacked transistor and the bias voltage node; and a fourth switch coupled between the gate of the second stacked transistor and the voltage rail.

Digital-to-analog converter (DAC) with dynamic stacked cascode switches

An apparatus, including: a switched capacitor configured to generate a switched capacitor voltage based on an input clock signal and a current; a current digital-to-analog converter (DAC) configured to generate the current based on a first digital signal; a first reference voltage generator configured to generate a first reference voltage; and a first voltage comparing device configured to generate a first frequency deviation detection signal based on a comparison of the switched capacitor voltage to the first reference voltage.

Clock frequency deviation detector with closed-loop calibration

Certain aspects of the present disclosure provide a relatively compact frequency-locked loop (FLL) using a discrete-time integrator. For certain aspects, the FLL also includes a supplemental oscillator and other circuitry that allows for saving the FLL frequency when a reference clock will be disconnected, maintaining a similar frequency during disconnection, and restoring the FLL frequency when the reference clock is reconnected. One example FLL circuit generally includes: an encoder; a combiner comprising a first input coupled to an output of the encoder; a digital-to-analog converter (DAC) comprising an input coupled to an output of the combiner; a discrete-time integrator comprising an input coupled to an output of the DAC; a voltage-controlled oscillator (VCO) comprising a control input coupled to an output of the discrete-time integrator; and a counter comprising an input coupled to an output of the VCO and comprising an output coupled to a second input of the combiner.

Compact frequency-locked loop architecture for digital clocking

A cascode bias circuit biases a gate of a cascode transistor in a cascode current mirror. The cascode bias circuit includes a first transistor configured to conduct a first current and includes a second transistor configured to conduct a second current. The first and second transistors couple to a third transistor configured to conduct a sum of the first current and the second current. A gate of the first transistor couples to a gate of the cascode transistor to bias the cascode transistor.

Low headroom cascode bias circuit for cascode current mirrors

Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) system. The DAC system generally includes a plurality of current steering cells, each comprising a current source coupled to at least two current steering switches, wherein control inputs of the at least two current steering switches are coupled to an input path of the DAC system. The DAC system may also include a current source toggle circuit configured to selectively disable the current source of at least one of the plurality of current steering cells, and a feedforward path coupled between the input path and at least one control input of the current source toggle circuit.

Digital amplitude tracking current steering digital-to-analog converter

Certain aspects of the present disclosure provide a digital-to-analog converter (DAC). The DAC generally includes a plurality of current-steering cells, each having a bypass switch, and a resistor ladder circuit having multiple segments. Each segment may include a first resistive element and a second resistive element, the bypass switch being configured to selectively provide a bypass current to a common node between the first resistive element and the second resistive element.

Digital-to-analog converter (DAC) with common-mode correction

Certain aspects of the present disclosure provide apparatus and techniques for digital-to-analog conversion. One example apparatus generally includes a first digital-to-analog converter (DAC) having an input coupled to a digital input node of the apparatus, a second DAC, a digital processor coupled between the digital input node and an input of the second DAC, and a combiner coupled to the first DAC and the second DAC.

Partitioned digital-to-analog converter system

Certain aspects of the present disclosure are directed to a digital-to-analog converter (DAC) system. The DAC system generally includes a first current-steering DAC having a positive output, a negative output, and a bypass output; a common-mode (CM) path coupled between the positive and negative outputs; and a CM current compensation path coupled to the CM path.

An interleaved digital-to-analog converter (DAC) system may include a first sub-DAC and a second sub-DAC and may be configured to provide both a converter output signal and a calibration output signal. The converter output signal may be provided by adding the first sub-DAC output signal and the second sub-DAC output signal. The calibration output signal may be provided by subtracting one of the first and second sub-DAC output signals from the other. The calibration output signal may be used as feedback to adjust the phase of one of the sub-DACs relative to the other, to promote phase matching their output signals.

Image calibration for time-interleaved digital-to-analog converter

Certain aspects of the present disclosure provide a digital-to-analog converter (DAC). The DAC generally includes a plurality of transistors selectively coupled to an output of the DAC, and a biasing circuit coupled to gates of the plurality of transistors. The biasing circuit may include a first transistor having a gate coupled to a drain of the first transistor, a first buffer having an input coupled to the gate of the first transistor, a second transistor having a gate coupled to an output of the first buffer, a first resistive-capacitive (RC) circuit having a first resistive element and a first capacitive element, the first RC circuit being coupled between the gate of the first transistor and the gate of the second transistor, and a first switch coupled between the first resistive element and the first capacitive element.

Digital-to-analog converter (DAC) design with reduced settling time

The present disclosure describes aspects of segmented resistor architecture for digital-to-analog converters (DACs). In some aspects, a DAC circuit is implemented with a first resistor network coupled to a set of binary code-controlled current sources and a second resistor network that includes a resistor coupled between the first resistor network and an output of the DAC circuit. A set of thermometer code-controlled current sources are coupled to a node of the second resistor network and provide varying amounts of current. This current is scaled based on a resistance of the second resistor network's resistor, which is higher than a resistance of the first resistor network and effective to increase a combined output impedance of the first and second resistor networks. The increase of output impedance reduces noise of the resistor networks that transfers to the output of the DAC circuit, thereby improving signal-to-noise performance of the DAC circuit.

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San Diego, CA, United States of America

Andrew Weil