Advanced Micro Devices Corporation

Andrew W Steinbach

Brian E Longhenry

Jason R Talbert

Ravi B Bingi

Ranger H Lam

Pravind K Hurry

Jeff H Gruger

Christopher Eric Tressler

Joe A Ricks

Michael G Drake

An apparatus includes a printed circuit board including a connector footprint comprising a first footprint portion operative to receive a first connector portion and a second footprint portion operative to receive a second connector portion. The first footprint portion is compliant with a first communications link type and the first and second footprint portions are jointly compliant with a second communications link type. The printed circuit board includes first conductive traces coupled to the first footprint portion and a first device footprint. The first conductive traces are selectively configurable according to a selected one of the first and second communications link types. The printed circuit board includes a second conductive traces coupled to the second footprint portion and the first device footprint. in at least one embodiment of the apparatus, the first communications link type is AC-coupled and the second communications link type is DC-coupled.

Slot design for flexible and expandable system architecture

An apparatus includes a printed circuit board including a connector footprint comprising a first footprint portion operative to receive a first connector portion and a second footprint portion operative to receive a second connector portion. The first footprint portion is compliant with a first communications link type and the first and second footprint portions are jointly compliant with a second communications link type. The printed circuit board includes first conductive traces coupled to the first footprint portion and a first device footprint. The first conductive traces are selectively configurable according to a selected one of the first and second communications link types. The printed circuit board includes a second conductive traces coupled to the second footprint portion and the first device footprint. In at least one embodiment of the apparatus, the first communications link type is AC-coupled and the second communications link type is DC-coupled.

An improved method of preventing computer malfunction during a change of power consumption states is disclosed. The computer operates a microprocessor at a specified voltage during a normal operation. To offset the normal decrease in voltage due to an instantaneous increase in power requirements during a change of power consumption states, the specified voltage is increased prior to entering a higher power consumption state such that the voltage level remains within minimum operating limits.

Method of preventing computer malfunction during a change of power consumption states via dynamic adjustment of core voltage

A system and method are presented for transmitting data upon an address portion of a computer system bus during periods of maximum or near-maximum utilization of a data portion of the bus. One embodiment of the computer system includes at least one central processing unit (CPU) and a main memory coupled to a processor bus. The main memory stores data, and the CPU executes instructions stored within the main memory. The processor bus is a split transaction bus. The processor bus is divided into an address bus, a data bus, and a control bus including address, data, and control signal lines, respectively. The CPU and the main memory each include a bus interface, and are coupled to the processor bus via the bus interface. The bus interface includes a transaction queue coupled to an interface unit. The interface unit is coupled to the address, data, and control buses, and performs bus transactions (i.e., read and/or write transactions) upon the processor bus. The split bus transactions are coordinated using tag values generated by the CPU. The transaction queue stores a list of pending data exchange operations. Each interface unit competes for control of the address and data buses. When the transaction queue is not full, the interface unit performs data transfers using the data bus. When the transaction queue is full (e.g., when the data bus is nearing maximum utilization), the interface unit is configured to gain control of the address bus and to transfer data via the address bus.

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Austin, TX, United States of America

Andrew W Steinbach