Intel Corporation

Andrew W Ott

Grant M Kloster

Sean W King

Jihperng Leu

Lawrence D Wong

Ajay K Sharma

Patrick R Morrow

Valery M Dubin

Michael D Goodner

Robert P Meagley

Stephen T Chambers

Jennifer O'Loughlin

Christine Hau-Riege

Michael L McSwiney

Dennis G Hanken

Bruce J Tufts

Bob E Leet

Patrick Marrow

In one aspect, an apparatus may include a metal gate of a transistor. An etch stop layer may be selectively formed over the metal gate. The etch stop layer may include a metal compound. An insulating layer may be over the etch stop layer. A conductive structure may be included through the insulating layer to the metal gate. Methods of making such transistors are also disclosed.

Transistor having an etch stop layer including a metal compound that is selectively formed over a metal gate, and method therefor

Transistor having an etch stop layer including a metal compound that is selectively formed over a metal gate

Methods and apparatuses to selectively deposit a dielectric on a self-assembled monolayer ('SAM') adsorbed metal are described. A wafer includes a device having a first electrode. A first self-assembled monolayer is deposited on the wafer covering the first electrode. Next, a portion of the first self-assembled monolayer is removed to expose the first electrode. The first self-assembled monolayer includes a hydrophobic layer. Further, second self-assembled monolayer is deposited on the first electrode. The second self-assembled monolayer includes a hydrophilic layer. Next, an insulating layer is deposited on the second self-assembled monolayer. Further, self-aligned contacts to one or more second electrodes of the device are formed.

Selective deposition of a dielectric on a self-assembled monolayer-adsorbed metal

A method and apparatus are provided an interconnect cladding layer. In one embodiment, a first sacrificial layer is deposited over a substrate and patterned. In the vias created during the patterning operation, a conductive material is placed to create conductive interconnects. After planarizing the conductive material, the sacrificial layer is removed leaving the interconnect exposed. A cladding layer is then deposited over the conductive material.

Method of making semiconductor device using a novel interconnect cladding layer

Embodiments of the invention provide a device with a hard mask layer between first and second ILD layers. The hard mask layer may have a k value approximately equal to the first and/or second ILD layers.

Integrated low-k hard mask

In one embodiment, the present invention includes introducing a conventional precursor and an organic precursor having an organic porogen into a vapor deposition apparatus; and forming a dielectric layer having the organic porogen on a substrate within the vapor deposition apparatus from the precursors. In certain embodiments, at least a portion of the organic porogen may be removed after subsequent processing, such as dual damascene processing.

Forming a dielectric layer using porogens

The invention relates to a microelectronic device and a structure therein that includes a diffusion barrier layer having a first thickness and a first dielectric constant. An etch stop layer is disposed above and on the diffusion barrier layer. The etch stop layer has a second thickness and a second dielectric constant.

Structure in a microelectronic device including a bi-layer for a diffusion barrier and an etch-stop layer

In one embodiment, the present invention includes introducing a precursor containing hydrocarbon substituents and optionally a second conventional or hydrocarbon-containing precursor into a vapor deposition apparatus; and forming a dielectric layer having the hydrocarbon substituents on a substrate within the vapor deposition apparatus from the precursor(s). In certain embodiments, at least a portion of the hydrocarbon substituents may be later removed from the dielectric layer to reduce density thereof.

Forming a dielectric layer using a hydrocarbon-containing precursor

A method, apparatus, system, and machine-readable medium for an interconnect structure in a semiconductor device and its method of formation is disclosed. Embodiments comprise a carbon-doped and silicon-doped interconnect having a concentration of silicon to avoid to forming a copper silicide layer between an interconnect and a passivation layer. Some embodiments provide unexpected results in electromigration reliability in regards to activation energy and/or mean time to failure.

Enhancement of an interconnect

A dual-damascene process where first alternate ILDs are made of a first material and second alternate ILDs are made of a second material. Each material is etchable at a faster rate than the other in the presence of different etchant such as for an organic polymer and an inorganic low k material. This allows the ILDs to be deposited alternately on one another without an etchant stop layer thereby reducing capacitance.

Dual-damascene interconnects without an etch stop layer by alternating ILDs

The present invention discloses a method including: determining whether a surface of a dielectric layer is reactive; activating the surface if the surface is not reactive; performing a cycle on the surface, the cycle including: reacting the surface with a metal; and activating the metal. The present invention also discloses a structure including: a substrate; a first interlayer dielectric located over the substrate; a first adhesion promoter layer located over the first interlayer dielectric; an etch stop layer located over the first adhesion promoter layer; a second adhesion promoter layer located over the etch stop layer; and a second interlayer dielectric located over the second adhesion promoter layer.

Adhesion between dielectric materials

A method for operating a multi-station processing chamber is described. A wafer is loaded onto the first station then indexed to the second station prior to processing. The indexing causes the wafer to be well-seated on it spindle before being processed. This prevents an improperly seated wafer from being processed at the first station.

Growing community of inventors

Hillsboro, OR, United States of America

Andrew W Ott