Blackberry Corporation

Nxp USA, Inc.

Andrew Vladimir Claude Cervin

Marina Zelner

Edward Horne

Susan Nagy

Mircea Capanu

Atin J Patel

Mark Vandermeulen

Ivoyl Koutsaroff

Edward Provo Wallis Horne

Paul Bun Cheuk Woo

James DiLorenzo

A process that incorporates teachings of the subject disclosure may include, for example, providing a first silicon dioxide layer on the silicon substrate, depositing a modifier layer on the first silicon dioxide layer, depositing a second silicon dioxide layer on the modifier layer to form a multilayer initial oxide and annealing the multilayer initial oxide resulting in an annealed multilayer initial oxide. The annealing causes diffusion of modifier species from the modifier layer into the first and second silicon dioxide layers and results in amorphous polysilicates. The first and second silicon dioxide layers have thicknesses that prevent the diffusion of the modifier species from reaching top and bottom interfaces of the annealed multilayer initial oxide. Other embodiments are disclosed.

Method and apparatus for compensating for high Thermal Expansion Coefficient mismatch of a stacked device

A system that incorporates teachings of the subject disclosure may include, for example, a thin film capacitor a silicon substrate having a silicon dioxide layer; an adhesion layer on the silicon dioxide layer, wherein the adhesion layer is a polar dielectric; a first electrode layer on the adhesion layer; a dielectric layer on the first electrode layer; and a second electrode layer on the dielectric layer. Other embodiments are disclosed.

Method and apparatus for a thin film dielectric stack

Aspects of the subject disclosure may include, for example, a method in which a selection is made for a first major constituent, a second major constituent and a minor constituent for forming a desired material. The method can include mixing the first major constituent, the second major constituent and the minor constituent in a single mixing step to provide a mixture of constituents. The method can include drying the mixture of constituents to provide a dried mixture of constituents and calcining the dried mixture of constituents to provide a calcinated mixture of constituents. The method can include processing the calcinated mixture of constituents (by a process including vacuum annealing and hot-pressing) to provide a sputtering target. Other embodiments are disclosed.

Method of forming a sputtering target

A device that incorporates teachings of the subject disclosure may include, for example, a multilayer initial oxide on a silicon substrate, where the multilayer initial oxide comprises amorphous polysilicates and a group one metal or a group two metal; a first electrode layer on the multilayer initial oxide; a dielectric layer on the first electrode layer; a second electrode layer on the dielectric layer, where an edge alignment spacing between at least one pair of corresponding electrode edges of two electrode layers of the capacitor is two microns or less; and connections for the first and second electrode layers. Other embodiments are disclosed.

Method and apparatus for compensating for high thermal expansion coefficient mismatch of a stacked device

A tunable capacitor that incorporates teachings of the subject disclosure may include: a substrate; a first dielectric layer over the substrate; a plurality of bias lines encapsulated between the substrate and the tunable dielectric layer; a first metal layer over the tunable dielectric layer (wherein the first metal layer has a plurality of first gaps); an upper bias layer over the first metal layer (herein each of a plurality of portions of the upper bias layer extend through a respective one of the plurality of first gaps to come into contact with the first dielectric layer, and wherein at least a second gap is disposed in the upper bias layer); and a second metal layer (wherein a portion of the second metal layer extends through the second gap to come into contact with the first metal layer). Other embodiments are disclosed.

Tunable coplanar capacitor with vertical tuning and lateral RF path and methods for manufacturing thereof

A coplanar capacitor that incorporates teachings of the subject disclosure may include: a substrate; a voltage-tunable dielectric layer over the substrate; a plurality of bias lines over the voltage-tunable dielectric layer (wherein the bias lines are covered by an inter-level dielectric); a plurality of sidewall spacers (wherein each of the sidewall spacers is located adjacent one of the bias lines and each of the sidewall spacers spans between a respective portion of the voltage-tunable dielectric layer and a respective portion of the inter-level dielectric); and an electrode over the inter-level dielectric, and over portions of the voltage-tunable dielectric layer that are not covered by the plurality of bias lines and that are not covered by the sidewall spacers, wherein a plurality of gaps are disposed in the electrode. Other embodiments are disclosed.

Small-gap coplanar tunable capacitors and methods for manufacturing thereof

A system that incorporates teachings of the subject disclosure may include, for example, a thin film capacitor having a substrate, a first electrode layer on the substrate, a first dielectric layer on the first electrode layer where the first dielectric layer has a columnar-oriented grain structure, a group of second dielectric layers stacked on the first dielectric layer where each of the group of second dielectric layers has a randomly-oriented grain structure, and a second electrode layer on the group of second dielectric layers. Other embodiments are disclosed.

A system that incorporates teachings of the subject disclosure may include, for example, a fabricated thin film capacitor formed by depositing a first dielectric layer on a first electrode layer utilizing a first process that is performed at a first temperature, depositing a second dielectric layer on the first dielectric layer utilizing a second process that forms a randomly-oriented grain structure for the second dielectric layer, depositing a third dielectric layer on the second dielectric layer utilizing a third process that is performed at a second temperature and that forms a columnar-oriented grain structure for the third dielectric layer where the second temperature is higher than the first temperature, and depositing a second electrode layer on the third dielectric layer to form the thin film capacitor. Other embodiments are disclosed.

Thin film dielectric stack

High-throughput deposition of a voltage-tunable dielectric material onto a substrate comprising a conductive electrode is provided. Respective gradients in at least two grain size defining parameters of the deposition are simultaneously provided, the respective gradients occurring for a first time period thereby producing a smoothly changing columnar crystalline habit of the voltage-tunable dielectric material. When the first time period has ended, the deposition continues for a second time period where the grain size defining parameters are held constant. In particular, the smoothly changing columnar crystalline habit of the voltage-tunable dielectric material is intentionally distorted by simultaneously providing the respective gradients in the in at least two grain size defining parameters of the deposition.

High-throughput deposition of a voltage-tunable dielectric material

A system that incorporates teachings of the subject disclosure may include, for example, a method in which a selection is made for a first major constituent, a second major constituent and a minor constituent for forming a desired material. The method can include mixing the first major constituent, the second major constituent and the minor constituent in a single mixing step to provide a mixture of constituents. The method can include drying the mixture of constituents to provide a dried mixture of constituents and calcining the dried mixture of constituents to provide a calcinated mixture of constituents. The method can include processing the calcinated mixture of constituents to provide a powder of constituents. Other embodiments are disclosed.

Method of forming a target for deposition of doped dielectric films by sputtering

A multi-layered capacitor includes three or more capacitor layers. A first layer includes a first DC-biased, tunable capacitor. A second layer, acoustically coupled to the first layer, includes a second DC-biased, tunable capacitor. A third layer, acoustically coupled to the second layer, includes a third DC-biased, tunable capacitor. Each dielectric of the first, second, and third capacitors has a resonance of about the same frequency, within 5%, and inner electrodes of the first, second, and third capacitors have a resonance of about the same frequency, within 5%. The resonance of each layer is a function of at least thickness, density, and material. The first, second, and third layers are biased to generate destructive acoustic interference, and the multi-layer capacitor is operable at frequencies greater than 0.1 GHz.

Electrostrictive resonance suppression for tunable capacitors

In accordance with the teachings described herein, a multi-level thin film capacitor on a ceramic substrate and method of manufacturing the same are provided. The multi-level thin film capacitor (MLC) may include at least one high permittivity dielectric layer between at least two electrode layers, the electrode layers being formed from a conductive thin film material. A buffer layer may be included between the ceramic substrate and the thin film MLC. The buffer layer may have a smooth surface with a surface roughness (Ra) less than or equal to 0.08 micrometers (um).

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Oakville, Canada

Andrew Vladimir Claude Cervin